需要读取128个8位数据，读取完成后将其组合为1024位的RAM并赋值给dout。ram_cnt会从0计数到65535，每累计128个数据（如0_127、128255区间）时，就将RAM数据赋值给dout。但波形显示异常：当ram_cnt=0时，di应为-15，RAM应呈现...X,X,X,-15的状态。

Data_buffer模块 #

module Data_buffer (
  clk,
  rst,
  we,
  en,
  addr,
  xw_data_128_done,
  di,
  dout,
  xw_bram_addr
);

output reg[11:0] xw_bram_addr;
output reg xw_data_128_done;
input clk, we, rst, en;
input [11:0] addr;
input signed [7:0] di;
output reg [1023:0] dout;

reg signed [7:0] RAM [127:0];
reg [7:0] ram_cnt;
reg first_write_xw_addr_to_bram;
reg xw_done_flag;
integer i;

always @(posedge clk) begin
  if (rst) begin
    dout <= 1024'b0;
    ram_cnt <= 0;
    xw_bram_addr <= 0;
    xw_data_128_done <= 0;
    first_write_xw_addr_to_bram <= 0;
    xw_done_flag <= 0;
  end else if (we && en) begin
    RAM[ram_cnt % 128] <= di;
    xw_done_flag <= 0;

    if ((ram_cnt != 0) && ((ram_cnt + 1) % 128 == 0)) begin
      for (i = 0; i < 128; i = i + 1) begin
        dout[(127 - i) * 8 +: 8] <= RAM[i];
      end
      xw_data_128_done <= 1;
      xw_done_flag <= 1;

      if (!first_write_xw_addr_to_bram) begin
        first_write_xw_addr_to_bram <= 1;
      end else begin
        xw_bram_addr <= xw_bram_addr + 1;
      end
    end
    ram_cnt <= ram_cnt + 1;
  end else if (xw_done_flag) begin
    xw_data_128_done <= 0;
    xw_done_flag <= 0;
  end
end

endmodule

Test Bench测试平台 #

module test_bench;

  reg clk;
  reg rst;
  reg we;
  reg en;
  reg [11:0] addr;
  reg signed [7:0] di;
  wire [1023:0] dout;
  wire [11:0] xw_bram_addr;
  wire xw_data_128_done;

  integer fp_r_source_xw;
  integer i, tmp_xw;
  reg signed [7:0] data_xw [0:2559];
  reg [11:0] cnt_xw;

  // Instantiate the Data_buffer module
  Data_buffer UUT (
    .clk(clk),
    .rst(rst),
    .we(we),
    .en(en),
    .addr(addr),
    .di(di),
    .dout(dout),
    .xw_bram_addr(xw_bram_addr),
    .xw_data_128_done(xw_data_128_done)
  );

  // Clock generation
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  // Initialize and read data from file
  initial begin
    fp_r_source_xw = $fopen("C:/LSTM_hardware/8bit_sim/project_1.srcs/sim_1/imports/xsim/it_xw_512_8bit.txt", "r");
    i = 0;
    while (!$feof(fp_r_source_xw) && i < 2560) begin
      tmp_xw = $fscanf(fp_r_source_xw, "%d", data_xw[i]);
      i = i + 1;
    end
    $fclose(fp_r_source_xw);
  end

  // Address and data loading logic
  always @(posedge clk) begin
    if (rst) begin
      addr <= 0;
      cnt_xw <= 0;
    end else if (en && we) begin
      if (cnt_xw < 2560) begin
        di <= data_xw[cnt_xw];
        addr <= cnt_xw % 128;
        cnt_xw <= cnt_xw + 1;
      end
    end
  end

  // Test sequence
  initial begin
    rst = 1;
    we = 0;
    en = 0;
    #20;

    rst = 0;
    #10;

    en = 1;
    we = 1;

    wait (xw_data_128_done == 1);

    we = 0;
    en = 0;
    #20;

    $stop;
  end

endmodule

内容的提问来源于stack exchange，提问作者Vina