你遇到的第一个时钟周期输出UUUUUUUU的问题，核心原因是VHDL中信号赋值的延迟特性——信号赋值语句并不会在执行时立即更新信号值，而是要等到当前进程结束后才会生效。在你的原始代码里，第一个时钟上升沿到来时：

1. 执行mem_value <= mem(counter)，但mem_value此时还是初始的未赋值状态（表现为U）；
2. 后续判断mem_value = "11111111"和给valor赋值时，用的都是这个未初始化的U值，最终导致输出异常。

下面给你两种可行的修改方案：

方案一：直接使用ROM索引值（最简洁） #

去掉中间信号mem_value，直接用mem(counter)完成判断和赋值，这样就能在同一个时钟沿内直接拿到当前计数器对应的ROM真实值：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity memoria is 
Port ( 
    clock, reset :in STD_LOGIC; 
    valor : out STD_LOGIC_VECTOR(7 downto 0); 
    vazia : out STD_LOGIC
); 
end memoria; 

architecture Behavioral of memoria is 
    type ROM is array (0 to 4) of STD_LOGIC_VECTOR(7 downto 0); 
    constant mem : ROM := (b"00000000", b"00000001", b"00000010", b"00000011", b"11111111");
begin 
    process(clock, reset)
        variable counter : integer := 0;
    begin 
        if reset = '1' then 
            valor <= "11111111";
            vazia <= '1';
        elsif clock'event and clock = '1' then 
            -- 直接使用mem(counter)，跳过延迟的信号赋值
            if mem(counter) = "11111111" then 
                vazia <= '1';
            else 
                vazia <= '0';
            end if;
            valor <= mem(counter);
            
            if counter < 4 then 
                counter := counter + 1;
            end if;
        else 
            valor <= "11111111";
            vazia <= '0';
        end if;
    end process;
end Behavioral;

方案二：将mem_value改为变量（保留中间值逻辑） #

如果需要保留中间值的逻辑，可以把mem_value从信号改成变量——变量赋值是立即生效的，能在同一个时钟沿内拿到最新值：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity memoria is 
Port ( 
    clock, reset :in STD_LOGIC; 
    valor : out STD_LOGIC_VECTOR(7 downto 0); 
    vazia : out STD_LOGIC
); 
end memoria; 

architecture Behavioral of memoria is 
    type ROM is array (0 to 4) of STD_LOGIC_VECTOR(7 downto 0); 
    constant mem : ROM := (b"00000000", b"00000001", b"00000010", b"00000011", b"11111111");
begin 
    process(clock, reset)
        variable counter : integer := 0;
        variable mem_value : STD_LOGIC_VECTOR(7 downto 0); -- 改为变量
    begin 
        if reset = '1' then 
            valor <= "11111111";
            vazia <= '1';
            counter := 0;
            mem_value := "11111111"; -- 初始化变量
        elsif clock'event and clock = '1' then 
            mem_value := mem(counter); -- 变量立即赋值
            if mem_value = "11111111" then 
                vazia <= '1';
            else 
                vazia <= '0';
            end if;
            valor <= mem_value;
            
            if counter < 4 then 
                counter := counter + 1;
            end if;
        else 
            valor <= "11111111";
            vazia <= '0';
        end if;
    end process;
end Behavioral;

测试平台补充优化 #

另外你的测试平台缺少复位触发逻辑，建议添加一段复位激励，确保电路从已知状态开始工作：

ENTITY memoria_tb IS 
END memoria_tb; 

ARCHITECTURE behavior OF memoria_tb IS 
    signal clock : std_logic;
    signal reset : std_logic := '0'; 
    signal valor : std_logic_vector(7 downto 0);
    signal vazia : std_logic; 
    constant clock_period : time := 10 ns; 
BEGIN 
    uut: entity work.memoria 
    PORT MAP ( 
        clock => clock, 
        reset => reset, 
        valor => valor, 
        vazia => vazia 
    ); 

    clock_process :process 
    begin 
        clock <= '0';
        wait for clock_period/2;
        clock <= '1';
        wait for clock_period/2;
    end process;

    -- 添加复位激励
    stim_proc: process
    begin
        reset <= '1';
        wait for 20 ns; -- 保持复位2个时钟周期
        reset <= '0';
        wait;
    end process;
END;

内容的提问来源于stack exchange，提问作者Jean Willian S. J.