First, let's recap the ACLK definition from the AXIS spec:

全局时钟信号。所有信号均在ACLK的上升沿被采样。

As noted, this assumes AXIS master and slave devices share the same ACLK. Now let's address your three questions one by one:

1) Is my understanding correct that ACLK slew rate issues between master/slave modules are the designer's responsibility, with no restrictions set by the spec? #

Your understanding is 100% correct. The AXIS spec only defines the core sampling rule (signals are sampled on the rising edge of ACLK) but doesn't impose any constraints on the electrical characteristics of ACLK itself—things like slew rate, jitter, or clock skew fall under hardware implementation details. It's entirely up to the designer to ensure these meet the requirements of your target FPGA/ASIC process and board design. For example, you might need to optimize clock routing for impedance matching, use on-chip clock buffers to minimize skew, or adjust board layout to avoid excessive slew rate variations that could cause sampling errors.

2) Is the statement correct that data transmission should be center-aligned with ACLK, so developers need to make the AXIS master send data aligned to the clock center? #

Yes, this is a valid and industry-standard best practice—though to be precise, the core requirement is that the valid data window must fully cover the ACLK rising sampling edge. Center-aligning the data relative to ACLK is the most robust way to achieve this, as it maximizes both setup time and hold time margins, which drastically reduces the risk of sampling errors. Since AXIS assumes a shared clock, the master's output data must adhere to setup/hold time requirements relative to ACLK, and center alignment is the go-to approach to meet these requirements reliably.

3) How to implement ACLK-centric data transmission? In an FPGA, how to generate a new clock with a left-shifted phase relative to the global clock to align data to the clock center? #

In FPGAs, there are two primary, reliable methods to achieve data center alignment with a global clock:

Method 1: Use the FPGA's Clock Management Tile (CMT)

This is the standard, most precise approach. FPGAs like Xilinx (with MMCM/PLL blocks) or Intel (with PLL/CDR blocks) include dedicated clock management hardware that can generate phase-shifted versions of the input clock:

1. Feed your global clock into the CMT input.
2. Configure the CMT to output a clock with a 90-degree left phase shift (for a 50% duty cycle clock, this shift ensures the data center aligns perfectly with the original global clock's rising edge).
3. Use this phase-shifted clock to drive the AXIS master's transmit logic. The ACLK seen by the slave remains the original global clock, while the master's output data will be center-aligned relative to it.

Here's a simplified Verilog example for Xilinx Vivado:

// Instantiate an MMCM to generate the phase-shifted clock
mmcm_phase_shift u_mmcm (
    .clk_in1  (global_clk),    // Input global clock
    .clk_out1 (shifted_clk),   // 90-degree left-shifted clock
    .locked   (mmcm_locked)    // Lock status signal
);

// AXIS master: use shifted_clk for transmit logic, global_clk as ACLK
axis_master u_axis_master (
    .aclk          (global_clk),      // ACLK for the AXIS interface
    .tx_logic_clk  (shifted_clk),     // Phase-shifted clock for transmit logic
    // Other AXIS signals (tdata, tvalid, tready, etc.)...
);

Always verify setup/hold times with your FPGA's timing analysis tool (e.g., Vivado Timing Analyzer) to confirm margins are sufficient.

Method 2: Programmable Delay Lines

If CMT resources are limited or you don't need ultra-precise phase control, you can use the FPGA's internal programmable delay units (like Xilinx IDELAY/ODELAY or Intel DELAY_BLOCK) to delay the data path instead of shifting the clock. This adjusts the data's arrival time to align with the ACLK sampling edge. However, this method is less stable than CMTs, as delay values can vary with temperature and process variations, so it's typically a fallback option.

内容的提问来源于stack exchange，提问作者haykp