Let's dig into this vlog-13069 error you're facing—this is a straightforward syntax issue, and since you're coming from a Verilog background, it's likely tied to a small formatting or typo slip-up when writing your SystemVerilog module.

First, the core issue from the error message #

The error points to line 2 near Dividerr and says ModelSim was expecting either a ; or (. That tells us the compiler doesn't recognize how you've structured your module declaration at that line. Here are the most common fixes:

1. Check for a typo in your module name (and fix the declaration structure)
   First, double-check if Dividerr is intentional (the extra 'r' at the end). If it's a typo, correcting it might help, but even if it's deliberate, the problem is almost certainly how you've written the module declaration.

   In both Verilog and SystemVerilog, module declarations need to follow this structure:

   // Option 1: Module with ports
   module Dividerr (
       // Port definitions go here (e.g., input logic clk;)
   );
   // Module logic here
   endmodule
   
   // Option 2: Module with no ports
   module Dividerr;
   // Module logic here
   endmodule
   

   If your line 2 is just Dividerr floating on its own (without a ( or ; immediately after), that's exactly what triggers this error. For example, this invalid code will throw the same message:

   // Wrong!
   module
   Dividerr
       input clk;
   endmodule
   

2. Ensure you're using valid SystemVerilog port syntax
   Since you're familiar with Verilog, note that SystemVerilog allows more concise port declarations (though Verilog-style is still supported). For example, SV lets you declare port direction and type in one line inside the parentheses:

   module Dividerr (
       input  logic        clk,
       input  logic        reset_n,
       input  logic [7:0]  dividend,
       output logic [7:0]  quotient
   );
   // ... logic ...
   endmodule
   

   If you're mixing old Verilog port styles with SV, make sure you're not missing commas or semicolons in the port list—those small omissions can also trigger this syntax error.

3. Verify your compilation setup
   Make sure you're compiling the file as SystemVerilog in ModelSim:

   • If using the GUI, right-click your .sv file and ensure the compile settings are set to SystemVerilog.
   • If using the command line, run vlog -sv q3.sv to explicitly tell the compiler to treat the file as SystemVerilog (instead of Verilog).

Quick note on writing your testbench #

Once you fix the module compilation, writing a SystemVerilog testbench is similar to Verilog, with some handy SV features you can leverage. Here's a simple template to get you started:

module tb_Dividerr;
    // Declare signals to connect to the DUT
    logic        clk;
    logic        reset_n;
    logic [7:0]  dividend;
    logic [7:0]  quotient;

    // Instantiate your Dividerr module
    Dividerr dut (
        .clk(clk),
        .reset_n(reset_n),
        .dividend(dividend),
        .quotient(quotient)
    );

    // Generate a 100MHz clock (5ns period)
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    // Test stimulus
    initial begin
        // Initialize signals
        reset_n = 0;
        dividend = 8'd0;
        #10 reset_n = 1; // Release reset

        // Drive test values
        #10 dividend = 8'd16;
        #20 dividend = 8'd32;
        #50 $finish; // End simulation
    end
endmodule

内容的提问来源于stack exchange，提问作者user8588899