Great questions—let’s break each one down with practical context and examples to make this concrete.

Short answer: Yes, definitely. While accumulator-only architectures rely on a single dedicated register for operand storage (which creates more potential data hazards compared to register-file ISAs), pipelining is still feasible with basic hardware workarounds.

For example, the Zilog Z80 (a classic accumulator-based 8-bit CPU) uses a simple 2-stage pipeline where it fetches the next instruction while executing the current one. Even with the accumulator being a shared resource, hardware can detect data dependencies (like an instruction writing to the accumulator followed by one reading from it) and either:

• Insert a small 1-cycle stall to wait for the write to complete, or
• Use basic data forwarding (if hardware supports it) to pass the accumulator’s updated value directly to the next stage without stalling.

The core of pipelining is breaking instruction execution into independent stages—accumulator architectures don’t block that, they just require handling more frequent data hazards.

Again, yes. The components you listed (accumulator, PC, MBR, IR, MAR, input/output registers) are exactly the building blocks needed for a basic pipeline. Let’s map them to a 3-stage workflow:

• Fetch: Use the PC to set the MAR, retrieve the instruction from memory into the MBR, then increment the PC for the next instruction.
• Decode: Move the instruction from the MBR to the IR, parse the opcode to determine the operation, and prepare operands (e.g., load a memory value to the accumulator, or read from the input register).
• Execute: Perform the operation using the accumulator, write results back to memory (via MAR/MBR), or send output to the output register.

These stages can overlap seamlessly: while one instruction is in Execute, the next is being Decoded, and the one after is being Fetched. The existing registers already act as buffers between stages, so no major hardware overhauls are needed here.

Which is more feasible with the given register set? #

The 3-stage (Fetch/Decode/Execute) pipeline is far more feasible with the components you described. A 5-stage pipeline typically splits the Execute phase into three smaller stages (e.g., Execute, Memory Access, Writeback), which requires extra dedicated registers to hold intermediate results (like an ALU output register to store values before writing back to the accumulator or memory). Since your architecture doesn’t include these extra registers, implementing a 5-stage pipeline would require adding new hardware—something the 3-stage setup avoids entirely.

Examples and theoretical possibilities #

• 3-stage examples: As mentioned earlier, the Z80 uses a quasi-3-stage pipeline (fetch overlaps with decode/execute), and the Intel 8086/8088 uses a similar 2-3 stage overlapping pipeline for accumulator-based operations. These are real-world implementations that prove 3-stage works with minimal register sets.
• 5-stage theoretical possibility: While it’s technically possible to implement a 5-stage pipeline with your base architecture, you’d need to add temporary registers (e.g., a buffer to hold ALU results during memory access, or a register to stage writes back to the accumulator). Without these, you’d have to force stages to share existing registers, which would create structural hazards and negate the benefits of pipelining. So it’s doable in theory, but not practical without modifying the original register set.

内容的提问来源于stack exchange，提问作者HotWheels