Great question—this is a common gotcha with SystemVerilog's event-driven simulation model that trips up even seasoned designers. Let's break down why you're seeing different hit counts, and how simulators handle these assign statements under the hood.

The Core Issue: Implicit Sensitivity Lists #

SystemVerilog continuous assignments (assign) use implicit sensitivity lists—meaning the simulator only evaluates the statement when any variable on the right-hand side (RHS) of the assignment changes. Even if two assignments share the same condition (_T_6), if their full RHS expressions include different variables, they'll be triggered by different events, leading to different hit counts.

Example to Illustrate #

Let’s say your code looks like this:

logic _T_6;
logic b, c;

// Assign 1: RHS includes _T_6, b, and c
wire a = _T_6 ? b : c;

// Assign 2: RHS only includes _T_6
wire d = _T_6 ? 1'b0 : 1'b1;

• When _T_6 changes, both assignments get evaluated (hit count for each increases by 1).
• When b or c changes, only the first assignment (a) gets re-evaluated—because those variables are part of its RHS. The second assignment (d) has no reason to run, since none of its RHS variables changed.
• Over time, the hit count for a will be higher than d, as it’s triggered by more events beyond just _T_6 changes.

Secondary Factor: Simulator Optimization #

Some simulators implement redundant evaluation elimination to boost performance. If the simulator detects that a change in an RHS variable won’t alter the final output of the assign statement, it might skip evaluating the statement entirely. For example:

• If _T_6 is 0, changing b won’t affect the value of a (since the ternary picks c instead). A smart simulator might skip evaluating a in this case, reducing its hit count compared to a simulator that evaluates every RHS variable change regardless of outcome.

This behavior is tool-specific, but it’s another possible reason for differing counts if your two assignments have similar RHS variables but different output dependencies.

What About Your Expectation? #

Your intuition that "_T_6 changes should trigger both statements" is partially correct—but only if _T_6 is the only variable driving both RHS expressions. The simulator doesn’t track conditions in isolation; it tracks all variables that could affect the assignment’s result.

Key Takeaways #

• Always remember that assign statements are event-driven, triggered by all variables in their RHS, not just the condition in a ternary or logical expression.
• To verify this, check the full RHS of both assignments—you’ll likely find extra variables in one that aren’t present in the other.
• If you need consistent evaluation counts, ensure both assignments have identical RHS variable sets (or use explicit procedural blocks like always_comb with identical sensitivity lists, though always_comb behaves similarly to assign in this regard).

内容的提问来源于stack exchange，提问作者yildizabdullah