Verilog新手求助：不使用generate实现模块实例并行迭代运行

我是Verilog完全新手，手里有一个块ROM模块CDbram_2_0_32，代码如下：

module CDbram_2_0_32 (clk, en, addr, dout);
input clk;
input en;
input [9:0] addr;
output [9:0] dout [0:37];

(*rom_style = "block" *) reg [9:0] data [0:37];

always @(posedge clk)
begin
if (en)
case(addr)
10'd0:data<={10'd19,10'd7,10'd27,-10'd1,10'd14,-10'd1,10'd11,10'd11,-10'd1,10'd19,-10'd1,10'd19,-10'd1,-10'd1,10'd28,10'd23,-10'd1,10'd12,-10'd1,10'd23,-10'd1,10'd4,-10'd1,10'd8,-10'd1,10'd18,-10'd1,-10'd1,10'd18,-10'd1,10'd19,-10'd1,10'd12,-10'd1,-10'd1,10'd15,-10'd1,-10'd1};
10'd1:data<={10'd22,10'd9,-10'd1,10'd1,10'd30,10'd11,10'd25,-10'd1,10'd31,10'd2,10'd19,-10'd1,10'd11,10'd30,-10'd1,10'd20,10'd26,-10'd1,10'd30,-10'd1,10'd14,-10'd1,-10'd1,-10'd1,10'd2,-10'd1,-10'd1,10'd10,-10'd1,-10'd1,-10'd1,10'd25,-10'd1,-10'd1,10'd31,-10'd1,-10'd1,10'd1};
10'd2:data<={-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,-10'd1,10'd31,-10'd1,10'd11,-10'd1,10'd29,-10'd1,10'd5,-10'd1,10'd7,-10'd1,-10'd1,10'd4,-10'd1,-10'd1,10'd6,-10'd1,-10'd1,-10'd1,10'd0,-10'd1};
....(and so on till addr 13)
endcase
end

assign dout = data;

endmodule

我的需求是：并行运行38个CN模块实例，ROM每个地址对应38个数据值，每个时钟上升沿，所有实例读取各自对应的dout[index]，然后把输出存入p2[index]，逻辑是p2[index] = p2[index]^p2_temp[index]。我写了一段示例代码，但肯定有问题：

for (j=0; j<14; j=j+1) begin: cn_instances
CN inst0 (.data_in(m[j]), .shift_amt(dout[0]), .data_out(p2_temp[0]));  assign p2[0] = p2[0]^p2_temp[0];

我知道普通for循环不能用来实例化模块，generate循环又会生成过多实例，这让我很困惑。我的完整代码如下：

`timescale 1ns / 1ps


module P2_inst (
    input clk,             // Clock signal
    input rst,             // Reset signal (active high)
    input en,              // Enable reading (active high)
    input [447:0] message,
    output reg [9:0] dout [0:13],  // Output data from ROM
    output reg [9:0] addr,          // Current address
    output reg [31:0] p2 [0:37]
);

reg [31:0] m [0:13];
assign {m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8], m[9], m[10], m[11], m[12], m[13] }= message;
reg [31:0] p2_temp [0:37];

CDbram_2_0_32 rom (
    .clk(clk),
    .en(en),       // Enable ROM read
    .addr(addr),   // Current address
    .dout(dout)    // Output data
);
always @(posedge clk or posedge rst) begin
    if (rst) begin
        addr <= 10'd0;  // Reset to address 0
    end
    else if (en) begin
        if (addr < 10'd531) begin  // Stop at last address (531)
        addr <= 10'd0;
genvar j;
for (j=0; j<14; j=j+1)begin: cn_instances
j<=addr;
CN inst0 (.data_in(m[j]), .shift_amt(dout[0]), .data_out(p2_temp[0]));  assign p2[0] = p2[0]^p2_temp[0];
CN inst1 (.data_in(m[j]), .shift_amt(dout[1]), .data_out(p2_temp[1]));  assign p2[1] = p2[1]^p2_temp[1];
....
CN inst37 (.data_in(m[j]), .shift_amt(dout[37]), .data_out(p2_temp[37]));  assign p2[37] = p2[37]^p2_temp[37];

        end
        else begin
            addr <= 10'd0;   // Wrap around (optional)
        end
    end
end

endmodule

恳请各位提供帮助。

内容的提问来源于stack exchange，提问作者Dara Greyest