Vivado与HDLBits仿真结果不一致问题排查求助

我正在学习Verilog，在HDLBits平台完成习题时，遇到了2014_q3fsm这道状态机题的问题。我根据状态转移图编写了如下Verilog代码：

module top_module(
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output reg z
);
    // State encoding
    parameter A = 3'd0, B1 = 3'd1, B2 = 3'd2, B3 = 3'd3, B = 3'd4;

    reg [2:0] state, next_state;
    reg [2:0] count;
    //reg z;
    
    // Next-state logic
    always @(*) begin
        case (state)
            A:  next_state = s ? B : A;
            B1: next_state = B2;
            B2: next_state = B3;
            B3: next_state = B;
            B: next_state = B1;
            default: next_state = A;
        endcase
    end

    // Sequential logic
    always @(posedge clk) begin
        if (reset) begin
            state <= A;
            count <= 0;
            z <= 0;
        end else begin
            state <= next_state;
            z <= 0;
            // Count update
            case (next_state)
                B : count <= 0;
                B1 : count <= w;
                B2: count <= count + w;
                B3: begin 
                    count <= count + w;
                    z <= (count + w == 2);
                end
                default: count <= 0;
            endcase
            
        end
    end
 
endmodule

提交后，HDLBits平台的结果显示我的输出z在t=120时变为1，但参考输出在t=110时就变为1。然而我在Vivado中运行如下测试代码：

module fsm1_tb;
    reg s, w, clk, reset;
    wire out, out2;
    top_module dut(clk, reset, s, w, out);

    always
        #5 clk = ~clk;
        
    initial begin
        clk = 1;
        reset = 1;
        s = 0;
        w = 0;
        #20 reset = 0;
        #20 s = 1;
        #10 w = 1;
        #30 w = 0;
        #5 w = 1;
        #10 w = 0;
        #5 w = 1;
        #10 w = 0;
        #5 w = 1;
        #5 w = 0;
        #5 w = 1;
        #5 w = 0;
        #5 w = 1;
        #10 w = 0;
        #25 $finish;
        
    end


    always @(posedge clk) begin
        $strobe("t=%0t: state=%d, next_state=%d, in=%b, count=%d", $time, dut.state, dut.next_state, w, dut.count);
    end
endmodule

得到的波形显示z在110ns时变为1。我不清楚为何会出现这种差异，想请教我的状态转移逻辑或代码是否存在问题？

内容的提问来源于stack exchange，提问作者qian li