Zephyr+NXP S32K344 LPUART14 DMA配置疑问及总线故障求助

1. DTS Configuration Verification #

Your DMA configuration in DTS is syntactically correct for Zephyr, but confirm these details to validate its validity:

• DMAMUX Slot Mapping: Per S32K344's reference manual, DMAMUX1 slot 46 is tied to LPUART14 TX, and slot 47 to LPUART14 RX. This matches hardware specifications.
• EDMA Channel Availability: Ensure EDMA channels 20 and 21 are not reserved by other peripherals (like SPI/I2C) in your DTS. No overlapping assignments are allowed.
• DMAMUX Controller Enable: Verify the dmamux1 node is enabled in your DTS. Zephyr's EDMA driver relies on this to link channels to their assigned slots.

If all checks pass, your DTS configuration is correct.

2. Resolving the BUS FAULT Error #

The fault's BFAR address (0x40254000) is LPUART14's base register address, meaning the error occurs when accessing this peripheral's registers. Follow these steps to fix it:

Debug & Fix Steps: #

• Check LPUART14 Clock Configuration:
  Confirm the LPUART14 node in DTS has valid clock-names and clocks properties pointing to an enabled clock source. A clock-gated peripheral will trigger a bus fault when accessed.

• Verify Peripheral Power Gating:
  Check the PMC (Power Management Controller) registers to ensure LPUART14 is not power-gated. Some peripherals require explicit un-gating via their PCR (Peripheral Control Register).

• Pinpoint Faulting Code:
  Use addr2line to map the faulting PC address (0x0040dc2c) to the exact source line in your Zephyr build:

  addr2line -e build/zephyr/zephyr.elf 0x0040dc2c
  

  This will reveal if the fault comes from a LPUART register write, DMA setup, or your callback code.

• Validate Callback Logic:
  In your BUFFER_REQUESTED callback:

  • Ensure you're using a valid, initialized pointer to the LPUART14 device (check with device_is_ready()).
  • Avoid direct register access; use Zephyr's UART API functions instead.
  • Confirm the peripheral is fully initialized before the callback is triggered.

• DMA Buffer Accessibility:
  While the BFAR points to LPUART14, ensure DMA buffers are in non-cacheable memory or that cache is flushed/invalidated before transfers. Stale cache data can cause unexpected behavior, even if it's not the direct fault cause here.

内容的提问来源于stack exchange，提问作者wh1sp3r