AMD/Intel CPU物理核心与逻辑核心：进程亲和性及架构疑问

Let’s tackle your questions one by one—CPU core naming and affinity can get tricky across different vendor architectures, so let’s clear up the confusion step by step.

Intel i3 Hyper-Threading & Core Affinity #

You’re spot-on with your initial assumption about the Intel i3:

• A typical dual-core i3 with Hyper-Threading (HT) has 2 physical cores, each split into 2 logical cores (total 4 logical cores).
• Setting process affinity to Core #0 binds the process to the first logical core of the first physical core.
• Core #1 is the second logical (Hyper-Threading) core belonging to that same first physical core.

Keep in mind these two logical cores share the physical core’s underlying resources (like execution units and cache), so they don’t perform like fully independent physical cores—great for light, thread-sparse tasks, but less ideal for heavy, parallel workloads.

AMD "Module" Architecture & Process Affinity #

AMD’s architecture has evolved a lot, so the best approach to affinity depends on the CPU generation:

Bulldozer/Piledriver (Old "Module" Era) #

These CPUs used a unique module design where each module contained 2 integer cores but shared a single floating-point unit (FPU) and L2 cache. For example, an 8-core Bulldozer CPU was actually 4 modules × 2 integer cores.

• For floating-point-heavy tasks: Avoid binding two processes to the same module’s integer cores—they’ll compete for the shared FPU, leading to worse performance. Instead, spread them across separate modules.
• For integer-only tasks: Same-module cores can work reasonably well together, as they don’t fight over the FPU.

Zen+ (Modern CCX/SMT Era) #

Starting with Zen, AMD switched to Core Complexes (CCX) where each CCX has 4-8 fully independent physical cores (each with its own FPU), and each core supports Simultaneous Multithreading (SMT—AMD’s equivalent of Intel HT, 2 logical cores per physical core).

• To optimize affinity:
  1. First, map your CPU’s core numbering to physical cores (use tools like CoreInfo on Windows or lscpu on Linux to visualize the topology).
  2. For single-threaded tasks: Bind to a single logical core (either of a physical core’s two threads—performance is nearly identical).
  3. For multi-threaded tasks: If you want maximum isolation, bind to separate physical cores (not just separate logical cores from the same physical core). Avoid spanning across CCXs if possible, as cross-CCX latency is higher.

On Windows, you can set affinity via Task Manager (Right-click process → Set affinity) or the start /affinity <mask> command. On Linux, use taskset <mask> <command>.

Is Intel’s HT Architecture Always 1 Physical Core = 2 Logical Cores? #

Yes, consistently since Intel first introduced Hyper-Threading with the Pentium 4. Every physical core with HT enabled will present exactly 2 logical cores to the OS. There are no exceptions in Intel’s consumer or server CPU lines—HT strictly follows a 1:2 physical-to-logical core ratio.

AMD’s Physical Core Architecture Evolution #

AMD’s core design has gone through three major phases:

• Bulldozer/Piledriver (2011–2015): Module-based, with shared FPU per module. Often marketed as "8-core" but had the floating-point throughput of 4 cores.
• Zen/Zen+ (2017–2019): CCX-based, 4 independent physical cores per CCX, each with its own FPU, plus SMT support. Shared L3 cache across the CCX.
• Zen 2/Zen 3/Zen 4 (2019–present): Chiplet-based design, with Core Chiplets (CCDs) containing 8 physical cores (Zen 2 split CCDs into two 4-core CCXs; Zen 3 unified CCDs into a single 8-core block). IO and memory controllers live on a separate IO Die, reducing latency for within-CCD tasks.

内容的提问来源于stack exchange，提问作者JonZ