Verilog仿真输出始终为x值问题求助（附模块及测试代码）

Hey Luis, let's dig into why your simulation is only showing x values for the Output signal—this is a common gotcha with Verilog combinational logic!

The Root Problem #

You’re using an initial block to calculate all those intermediate and/or signals in your Network_Router module, but initial blocks only run once at the very start of simulation (time 0). After that, even when your testbench updates the values of P/Q/R/S, those reg-type variables (like and1, or1, etc.) never get re-calculated—they stay stuck in their initial unknown (x) state. That’s why your Output always reads x too.

Fixed Module Code #

Combinational logic needs to re-run every time any input changes, so you should replace the initial block with an always @* block (this is the modern, clean way to trigger on all input updates). Here’s the corrected module:

module Network_Router (P, Q, R, S, Output); 
    input P, Q, R, S; 
    output Output; 
    wire Output; 
    reg and1, and2, and3, and4, and5, and6, or1, or2, or3, or4, or5; 

    // always @* triggers whenever any input (P/Q/R/S) changes
    always @* begin 
        and1 = P & Q; 
        and2 = Q & R; 
        or1 = and1 | and2; 
        and3 = P & R; 
        and4 = S & R; 
        or2 = and3 | and4; 
        or3 = or1 | or2; 
        and5 = Q & S; 
        and6 = P & S; 
        or4 = and5 | and6; 
        or5 = or3 | or4; 
    end 

    assign Output = or5; 
endmodule

Even Simpler Version (Optional) #

You can also skip all the intermediate variables entirely and compute Output directly with a single continuous assignment—this is more concise for straightforward combinational logic:

module Network_Router (P, Q, R, S, Output); 
    input P, Q, R, S; 
    output Output; 

    assign Output = (P&Q | Q&R) | (P&R | S&R) | (Q&S | P&S);
endmodule

Good News: Your Testbench is Perfect #

Your testbench setup is totally correct—it’s iterating through all possible input combinations and dumping waveforms properly. Once you update the module as above, your simulation will show valid 0/1 values for Output instead of x.

内容的提问来源于stack exchange，提问作者Luis Hernandez