ModelSim中Case语句引发仿真崩溃问题求助

Hey there, let's break down why ModelSim's crashing on that LUT lookup always block while your hardware works perfectly fine—this is a super common simulation vs. hardware quirk that trips up new (and even experienced!) FPGA devs.

The Root Cause #

Your always block doesn't have a sensitivity list. In hardware synthesis, tools like Quartus will automatically infer that this is combinational logic and add all relevant signals (in this case, LUT_INDEX) to the sensitivity list. But ModelSim treats an always block without a sensitivity list as an infinite loop: it keeps re-executing the block nonstop, updating LUT_DATA over and over until it eats up all your system memory and crashes.

Hardware runs combinational logic in parallel, so this isn't an issue on your board—but sequential simulators like ModelSim can't handle that unconstrained execution.

The Fix #

Rewrite the block to explicitly use a combinational sensitivity list with @(*), which tells ModelSim to only re-run the block when LUT_INDEX changes:

reg [15:0] LUT_DATA; 
reg [6:0] LUT_INDEX; 
parameter LUT_SIZE = 31; 

always @(*) begin // Add sensitivity list here
    case(LUT_INDEX) 
        // Video Config Data 
        0 : LUT_DATA <= 16'h9803; //Must be set to 0x03 for proper operation 
        1 : LUT_DATA <= 16'h0100; //Set 'N' value at 6144 
        2 : LUT_DATA <= 16'h0218; //Set 'N' value at 6144 
        3 : LUT_DATA <= 16'h0300; //Set 'N' value at 6144 
        4 : LUT_DATA <= 16'h1470; // Set Ch count in the channel status to 8. 
        5 : LUT_DATA <= 16'h1520; //Input 444 (RGB or YCrCb) with Separate Syncs, 48kHz fs 
        6 : LUT_DATA <= 16'h1630; //Output format 444, 24-bit input 
        7 : LUT_DATA <= 16'h1846; //Disable CSC 
        8 : LUT_DATA <= 16'h4080; //General control packet enable 
        9 : LUT_DATA <= 16'h4110; //Power down control 
        10 : LUT_DATA <= 16'h49A8; //Set dither mode - 12-to-10 bit 
        11 : LUT_DATA <= 16'h5510; //Set RGB in AVI infoframe 
        12 : LUT_DATA <= 16'h5608; //Set active format aspect 
        13 : LUT_DATA <= 16'h96F6; //Set interrup 
        14 : LUT_DATA <= 16'h7307; //Info frame Ch count to 8 
        15 : LUT_DATA <= 16'h761f; //Set speaker allocation for 8 channels 
        16 : LUT_DATA <= 16'h9803; //Must be set to 0x03 for proper operation 
        17 : LUT_DATA <= 16'h9902; //Must be set to Default Value 
        18 : LUT_DATA <= 16'h9ae0; //Must be set to 0b1110000 
        19 : LUT_DATA <= 16'h9c30; //PLL filter R1 value 
        20 : LUT_DATA <= 16'h9d61; //Set clock divide 
        21 : LUT_DATA <= 16'ha2a4; //Must be set to 0xA4 for proper operation 
        22 : LUT_DATA <= 16'ha3a4; //Must be set to 0xA4 for proper operation 
        23 : LUT_DATA <= 16'ha504; //Must be set to Default Value 
        24 : LUT_DATA <= 16'hab40; //Must be set to Default Value 
        25 : LUT_DATA <= 16'haf16; //Select HDMI mode 
        26 : LUT_DATA <= 16'hba60; //No clock delay 
        27 : LUT_DATA <= 16'hd1ff; //Must be set to Default Value 
        28 : LUT_DATA <= 16'hde10; //Must be set to Default for proper operation 
        29 : LUT_DATA <= 16'he460; //Must be set to Default Value 
        30 : LUT_DATA <= 16'hfa7d; //Nbr of times to look for good phase 
        default: LUT_DATA <= 16'h9803; 
    endcase 
end

Why This Works #

• @(*) automatically includes all signals that drive the logic inside the block (here, just LUT_INDEX), so ModelSim only runs the block when LUT_INDEX changes—no more infinite loops eating memory.
• This is also better practice for Verilog code: explicit sensitivity lists make your intent clear to both tools and other developers.

Quick Debug Tip #

If you ever run into similar simulation crashes in the future, try adding a $display statement inside the block to see how often it's executing. For this case, you'd see it spamming the console nonstop, which is a dead giveaway that you've got an unconstrained always block.

内容的提问来源于stack exchange，提问作者Ross F