VHDL信号初始化问题：输入TEMPERATURE赋值后temp仍为UU如何解决？

Ah, this is a classic VHDL pitfall! Let's break down what's happening and how to fix it:

The Root Cause #

When you use := to initialize a signal like this:

signal temp:STD_LOGIC_VECTOR(7 downto 0):=TEMPERATURE;

This initialization runs only once, at the very start of simulation/synthesis—before your input port TEMPERATURE has been driven by anything. In simulation, unconnected input ports default to the "UU" (uninitialized) state, so your temp gets stuck with that value forever unless you explicitly update it later.

The Fix: Use a Process to Update temp Dynamically #

Instead of relying on initial assignment, create a process that triggers whenever TEMPERATURE changes, and assign the port value to temp inside that process. This ensures temp always mirrors the current value of TEMPERATURE.

Here's how to adjust your code:

-- Your entity (unchanged)
entity YourEntity is
    port (
        TEMPERATURE: in STD_LOGIC_VECTOR(7 downto 0)
    );
end entity YourEntity;

architecture Behavioral of YourEntity is
    -- Remove the initial assignment from the signal declaration
    signal temp: STD_LOGIC_VECTOR(7 downto 0);
begin
    -- Process to update temp whenever TEMPERATURE changes
    update_temp: process(TEMPERATURE)
    begin
        temp <= TEMPERATURE;
    end process update_temp;

    -- Rest of your architecture code goes here
end architecture Behavioral;

Bonus: Ensure Your Input Port is Driven in Simulation #

If you still see "UU" after this fix, check your testbench! Input ports don't generate their own values—you need to drive TEMPERATURE from your testbench with an initial value (e.g., TEMPERATURE <= x"00"; at the start of simulation) to give temp a valid starting value.

内容的提问来源于stack exchange，提问作者user9785232