Lattice iCE40-HX8K FPGA JTAG识别失败问题求助

Hey there, let’s work through this JTAG issue step by step—starting out with FPGAs and custom JTAG setups can be tricky, but we’ll get it sorted.

First: Fix the urjtag Cable Command #

Your error starting with jtag> cable UsbBlaster Conne... suggests the cable configuration is off, especially with clone devices. Here’s what to try:

• For USB Blaster clones: Most clones use a different VID/PID than the original Altera device. Run lsusb on your PC to find your programmer’s vendor and product IDs (look for entries like Bus 001 Device 005: ID 0403:6010 Future Technology Devices International, Ltd FT2232H Dual USB-UART/FIFO IC). Then specify them in urjtag:

  jtag> cable UsbBlaster <VID> <PID>
  

  Example for an FT2232-based clone: cable UsbBlaster 0x0403 0x6010
• For DirtJTAG (STM32 BluePill): urjtag doesn’t natively support DirtJTAG as a "UsbBlaster"—you need to use the ST-Link compatible cable type instead. Try:

  jtag> cable stlink
  

  If that fails, check if your DirtJTAG firmware is up to date, and confirm the BluePill is connected to your PC via USB (not just JTAG to the FPGA board).

Hardware Checks (Critical for Olimex’s No-Pullup Design) #

You added 10kΩ pullups, but let’s verify they’re set up correctly:

• Only pull up TMS, TDI, TCK: TDO is an output from the FPGA, so it should not have a pullup. If you accidentally added one to TDO, remove it immediately—this can prevent the FPGA from sending data back.
• Pullup voltage: iCE40-HX8K is a 3.3V device—make sure your pullups are connected to 3.3V, not 5V. Using 5V here can damage the FPGA’s JTAG pins.
• Pin connections: Double-check every JTAG pin matches between your programmer and the Olimex board:
  • TCK ↔ TCK
  • TMS ↔ TMS
  • TDI ↔ TDI
  • TDO ↔ TDO
  • GND ↔ GND
    Even one swapped pin (like TMS and TCK) will break detection. Use a multimeter to test continuity between each pair.
• Power and reset: Ensure the Olimex board is receiving stable 3.3V power, and the FPGA’s reset pin is not held low. Many Olimex boards have a reset button—press it once before running detect in urjtag to make sure the FPGA is in a ready state.
• Soldering quality: Check your pullup resistors for cold solder joints or shorts. Use a multimeter to measure the resistance between each pulled-up pin and 3.3V—you should see ~10kΩ.

urjtag Compatibility & Workflow #

• Update urjtag: Older versions of urjtag may not have full support for the iCE40-HX8K. Install the latest version from your package manager or build it from source to ensure device support is included.
• Correct command flow: After setting the cable, run the detect command to scan the JTAG chain:

  jtag> detect
  

  If detect returns nothing, try the chain command to list connected devices. Sometimes chain is more verbose about partial detection.

Alternative: Try OpenOCD (If urjtag Continues to Fail) #

If urjtag still isn’t working, OpenOCD has better out-of-the-box support for iCE40 and clone JTAG programmers. You can create a simple config file for your setup and run:

openocd -f <your-config-file>.cfg

Then use GDB or OpenOCD’s telnet interface to interact with the FPGA.

内容的提问来源于stack exchange，提问作者JohnnySorocil