Verilog及SystemVerilog中浮点随机数生成的硬件实现问询

Great question! Let’s break this down clearly—covering both simulation workflows and actual hardware implementation, since those are two very different use cases.

SystemVerilog: The Straightforward Approach #

SystemVerilog simplifies this a lot because it natively supports real types and built-in randomization. You can directly declare a randomized real variable and add constraints to control its range, distribution, or other properties.

Here’s a quick example for simulation:

class FloatRandomizer;
  rand real float_val;
  
  // Constrain to a range of -100.0 to 100.0 (adjust as needed)
  constraint valid_range {
    float_val inside {[-100.0 : 100.0]};
  }
endclass

// Usage in a testbench
initial begin
  FloatRandomizer fr = new();
  repeat(10) begin
    if (!fr.randomize()) $fatal(1, "Randomization failed!");
    $display("Random float: %0.6f", fr.float_val);
  end
end

This works seamlessly in simulation, and you can even add more complex constraints (like targeting a normal distribution) using SystemVerilog’s advanced randomization features.

Verilog: Workarounds for Older Versions #

Standard Verilog (pre-SystemVerilog, like Verilog-2001) doesn’t have native support for randomized real types. You’ll need to roll your own solution with two common approaches:

1. Integer Random → Float Conversion #

Generate a signed integer random number, then scale it to your desired floating-point range using $itor() (integer-to-real conversion):

reg [31:0] rand_int;
real float_val;

initial begin
  repeat(10) begin
    rand_int = $random; // Generates a 32-bit signed integer (-2^31 to 2^31-1)
    // Scale to get a value in [-1.0, 1.0)
    float_val = $itor(rand_int) / 2147483648.0;
    $display("Random float: %0.6f", float_val);
  end
end

Adjust the divisor to change the range—for example, divide by 1073741824.0 to get [-2.0, 2.0).

2. Manual IEEE 754 Floating-Point Generation #

If you need to generate actual IEEE 754-encoded floating-point values (like 32-bit single-precision), you can randomize each component of the float separately:

reg [31:0] ieee_single_precision;
reg sign_bit;
reg [7:0] exp_bits;
reg [22:0] mantissa_bits;

initial begin
  repeat(10) begin
    sign_bit = $random; // 0 for positive, 1 for negative
    // Avoid NaN/infinity by excluding all-1s exponent; adjust range as needed
    exp_bits = $random % 255; // 0 to 254
    mantissa_bits = $random; // Random 23-bit mantissa
    
    // Assemble the IEEE 754 single-precision float
    ieee_single_precision = {sign_bit, exp_bits, mantissa_bits};
    // Convert to real for display
    $display("IEEE float: %h | Decimal: %0.6f", 
             ieee_single_precision, 
             $bitstoshortreal(ieee_single_precision));
  end
end

Note: If you want to avoid denormals too, constrain exp_bits to [1:254] instead of [0:254].

Hardware Implementation (FPGA/ASIC) #

If you need to generate floating-point random numbers in actual hardware (not just simulation), you’ll need a hardware-friendly design:

• Start with a Hardware RNG: Use an LFSR (Linear Feedback Shift Register) or XORSHIFT module—these are lightweight, easy to implement in hardware, and produce pseudo-random integers efficiently.
• Convert to IEEE 754: Map the RNG’s integer output to a floating-point format:
  • Sign bit: Use a single bit from the RNG, or a separate small LFSR, to randomize positive/negative values.
  • Exponent bits: Set or randomize these based on your desired range. For example, to generate values in [0,1), fix the exponent to 8'b01111110 (single-precision, since the exponent bias is 127—127-1=126).
  • Mantissa bits: Fill the mantissa with bits from the RNG, making sure to handle the hidden leading 1 (per IEEE 754 rules).
• Filter Special Values: Add logic to exclude NaNs, infinities, and denormals if needed—this means clamping the exponent to a valid range (not all 0s or all 1s).
• Optimize for Performance: Use pipelining or parallel RNGs if you need high-throughput random floats.

A simple hardware example for single-precision [0,1) floats:

• Sign bit: 1'b0 (fixed positive)
• Exponent: 8'b01111110 (fixed to get values <1)
• Mantissa: 23 bits from an LFSR
• Final 32-bit float: {1'b0, 8'b01111110, lfsr_output[22:0]}

Key Takeaways #

• SystemVerilog: Use rand real with constraints for simulation—this is the fastest, most maintainable approach.
• Verilog: Use integer-to-float conversion or manual IEEE 754 assembly when stuck with older Verilog versions.
• Hardware: Build around an LFSR/XORSHIFT RNG, then add logic to map the integer output to valid IEEE 754 floating-point values.

内容的提问来源于stack exchange，提问作者Harish Kumar