请求编写Altera DE2的part5组件ModelSim测试平台VHDL代码

Got it, let's put together a VHDL testbench for your part5 component and walk through how to validate it in ModelSim. Below is a complete implementation with explanations, plus steps to run the simulation.

测试平台核心思路 #

The testbench will:

• Simulate the 50MHz system clock (CLOCK_50)
• Mimic the KEY0 start trigger and KEY3 input (we'll assume KEY3 is high by default—adjust if it has a specific reset/control function)
• Feed different values to the SW input to verify the counter triggers the LED at the correct cycle count
• Monitor both the LEDR output and HEX displays (even if you didn't specify HEX functionality, including them helps debug counting behavior)

完整测试平台代码 #

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity part5_tb is
-- Testbenches don't require external ports
end part5_tb;

architecture Behavioral of part5_tb is

-- Declare the component we're testing
component part5 
PORT ( 
    CLOCK_50, KEY0, KEY3 : IN STD_LOGIC; 
    SW: IN STD_LOGIC_VECTOR (7 DOWNTO 0); 
    HEX3, HEX2, HEX1, HEX0: OUT STD_LOGIC_VECTOR (6 DOWNTO 0); 
    LEDR : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) 
); 
END COMPONENT;

-- Test signals mapped to the component
signal CLOCK_50_tb : STD_LOGIC := '0';
signal KEY0_tb     : STD_LOGIC := '0';
signal KEY3_tb     : STD_LOGIC := '1'; -- Adjust if KEY3 has a specific role
signal SW_tb       : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal HEX3_tb     : STD_LOGIC_VECTOR(6 DOWNTO 0);
signal HEX2_tb     : STD_LOGIC_VECTOR(6 DOWNTO 0);
signal HEX1_tb     : STD_LOGIC_VECTOR(6 DOWNTO 0);
signal HEX0_tb     : STD_LOGIC_VECTOR(6 DOWNTO 0);
signal LEDR_tb     : STD_LOGIC_VECTOR(1 DOWNTO 0);

-- 50MHz clock = 20ns period
constant CLK_PERIOD : TIME := 20 ns;

begin

-- Instantiate the unit under test (UUT)
uut: part5
port map(
    CLOCK_50 => CLOCK_50_tb,
    KEY0     => KEY0_tb,
    KEY3     => KEY3_tb,
    SW       => SW_tb,
    HEX3     => HEX3_tb,
    HEX2     => HEX2_tb,
    HEX1     => HEX1_tb,
    HEX0     => HEX0_tb,
    LEDR     => LEDR_tb
);

-- Generate the 50MHz clock signal
clk_process: process
begin
    CLOCK_50_tb <= '0';
    wait for CLK_PERIOD/2;
    CLOCK_50_tb <= '1';
    wait for CLK_PERIOD/2;
end process;

-- Test stimulus sequence
stim_process: process
begin
    -- Initial state: KEY0 low, SW set to 0
    KEY0_tb <= '0';
    SW_tb <= x"00";
    wait for 100 ns;
    
    -- Test 1: Count to 5 (SW = 0x05)
    SW_tb <= x"05";
    wait for 50 ns;
    KEY0_tb <= '1'; -- Trigger count start
    wait until LEDR_tb /= "00"; -- Wait for LED to activate
    report "Test 1 passed: LEDR activated after 5 clock cycles" severity note;
    wait for 100 ns;
    KEY0_tb <= '0';
    wait for 100 ns;
    
    -- Test 2: Count to max 8-bit value (255 cycles)
    SW_tb <= x"FF";
    wait for 50 ns;
    KEY0_tb <= '1';
    wait until LEDR_tb /= "00";
    report "Test 2 passed: LEDR activated after 255 clock cycles" severity note;
    wait for 100 ns;
    KEY0_tb <= '0';
    wait for 100 ns;
    
    -- Test 3: Verify reset/repeat functionality
    SW_tb <= x"10";
    wait for 50 ns;
    KEY0_tb <= '1';
    wait until LEDR_tb /= "00";
    report "Test 3 passed: First activation after 16 cycles" severity note;
    wait for 50 ns;
    KEY0_tb <= '0';
    wait for 50 ns;
    KEY0_tb <= '1'; -- Trigger count again
    wait until LEDR_tb /= "00";
    report "Test 3 passed: Second activation after 16 cycles" severity note;
    
    -- End simulation
    wait;
end process;

end Behavioral;

ModelSim仿真步骤 #

1. Setup the project: Open ModelSim, create a new project, and add both part5.vhd and part5_tb.vhd to it.
2. Compile files: Right-click each file and select "Compile" → "Compile Selected" (fix any syntax errors if they pop up).
3. Start simulation: Right-click the part5_tb entity in the project browser, then select "Simulate".
4. Add signals to waveform: Right-click the uut (unit under test) instance in the simulation window, choose "Add to Wave" → "All Items in Region".
5. Run simulation: Click the "Run" button in the toolbar, or type run -all in the transcript window to run until the testbench finishes.
6. Validate results:
   • Check the waveform to confirm LEDR_tb turns on exactly after the number of clock cycles specified by SW_tb.
   • Review the transcript window for the "Test passed" reports.
   • If your HEX displays show the current count, verify their values increment correctly until the target is hit.

Notes #

• If KEY3 acts as a reset, adjust the KEY3_tb signal in the stimulus process to toggle it and test reset functionality.
• If the LED doesn't activate as expected, double-check the counting logic in part5 (e.g., whether it starts counting on the rising edge of KEY0, or if it includes the trigger cycle in the count).

内容的提问来源于stack exchange，提问作者218141