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ARMv7中如何写入R14(LR链接寄存器)?中断加载0xFFFFFFF9遇阻求助

Fixing the "Can't Load 0xFFFFFFF9 to LR with MOV" Issue for ARM Interrupt Exit

Got it, let's break this down. On ARM architectures (especially older ARMv7-A/R cores), the value 0xFFFFFFF9 is the exception return address used to exit interrupts and return to Handler mode (with interrupts enabled). The problem with MOV here is that ARM's MOV instruction can't directly load 32-bit immediate values that don't fit its restricted format—only 8-bit values rotated by even positions are allowed. 0xFFFFFFF9 doesn't meet this criteria, hence the failure.

Here are three reliable workarounds, tailored to different scenarios:

  • Use the LDR Pseudo-Instruction (Simplest Approach)
    This is the most straightforward method, as the assembler handles the heavy lifting for you. It stores the target value in a nearby "literal pool" and generates a PC-relative load instruction:

    LDR LR, =0xFFFFFFF9  ; Assembler translates this to a PC-relative LDR
    BX LR                ; Trigger the exception return
    

    The pseudo-instruction LDR Rd, =imm automatically places 0xFFFFFFF9 in a readable memory location near your code, then loads it into LR without immediate value restrictions.

  • Build the Value with MOV + MVN
    Since 0xFFFFFFF9 is the bitwise NOT of 0x6, you can use the MVN (Move Not) instruction to construct it:

    MOV R0, #0x6         ; Load the 8-bit immediate that's the inverse of our target
    MVN LR, R0           ; LR = ~R0, which equals 0xFFFFFFF9
    BX LR
    

    This avoids accessing memory entirely, making it a good choice if you want a pure register-based solution.

  • Thumb Mode: Use MOVW + MOVT (ARMv6T2+)
    If your interrupt handler runs in Thumb mode, you can split the 32-bit value into two 16-bit halves and load them with MOVW (Move Wide) and MOVT (Move Top):

    MOVW LR, #0xFFF9     ; Load the lower 16 bits of 0xFFFFFFF9
    MOVT LR, #0xFFFF     ; Load the upper 16 bits
    BX LR
    

    This is clean for Thumb-2 environments and works without relying on a literal pool.

Just a quick reminder: Always double-check your core's exception return rules—0xFFFFFFF9 corresponds to returning to Handler mode with interrupts enabled (depending on your ARM version), so make sure this aligns with your system's requirements.

内容的提问来源于stack exchange,提问作者Jyothi Bhat

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最近更新时间:2026.05.19 09:52:38