通用n位行波进位加法器仿真输出无驱动致UU值问题求助

Hey Scott, let's break down why you're seeing those UUUUUUUU values and the vsim-8683 warning. That error is straightforward: your 8-bit s output port on the ripple carry adder isn't connected to any logic—it's floating, so the simulator can't resolve it to a valid 0/1 value, hence all U's.

Here are the most common fixes, ordered by likelihood:

1. Check if Your Ripple Carry Adder Connects FA Sum Outputs to the s Port #

This is the #1 culprit. It's easy to accidentally leave the sum port of your full-adder (FA) instances unconnected in the generate loop.

Example of the Mistake #

module ripple_carry_adder #(parameter N=8)(
    input [N-1:0] a, b,
    input cin,
    output [N-1:0] s,
    output cout
);

wire [N:0] carry;
assign carry[0] = cin;

genvar i;
generate
    for(i=0; i<N; i=i+1) begin
        FA fa_inst(
            .a(a[i]),
            .b(b[i]),
            .cin(carry[i]),
            .sum(),  // ❌ Sum port is left unconnected!
            .cout(carry[i+1])
        );
    end
endgenerate

assign cout = carry[N];

endmodule

The Fix #

You need to explicitly connect each FA's sum output to the corresponding bit of your s port:

module ripple_carry_adder #(parameter N=8)(
    input [N-1:0] a, b,
    input cin,
    output [N-1:0] s,
    output cout
);

wire [N:0] carry;
assign carry[0] = cin;

genvar i;
generate
    for(i=0; i<N; i=i+1) begin
        FA fa_inst(
            .a(a[i]),
            .b(b[i]),
            .cin(carry[i]),
            .sum(s[i]),  // ✅ Connect FA sum to s[i]
            .cout(carry[i+1])
        );
    end
endgenerate

assign cout = carry[N];

endmodule

2. Verify Your Full-Adder (FA) Module is Correct #

If the ripple carry adder is wired right, double-check your FA module to make sure the sum output is properly declared and assigned:

Example of a Broken FA #

// ❌ Broken FA: sum is declared as input, or no assignment
module FA(
    input a, b, cin,
    input sum,  // Wrong! sum should be an output
    output cout
);

wire temp1 = a ^ b;
assign cout = (a & b) | (cin & temp1);
// No assignment to sum!
endmodule

Correct FA Implementation #

// ✅ Working FA
module FA(
    input a, b, cin,
    output sum,
    output cout
);

// Directly assign sum and cout using combinational logic
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));

endmodule

3. Recompile All Modules Cleanly #

Sometimes simulators cache old compiled code. After fixing the connections:

• Delete any existing compiled libraries (in ModelSim, use vdel -all)
• Recompile your FA module first, then the ripple carry adder, then your testbench
• Restart the simulation

Once you make these fixes, your s port will have valid driven values instead of U's.

内容的提问来源于stack exchange，提问作者Scott