技术咨询：如何通过LabVIEW获取连接Xilinx Spartan 6的CY7C68013A-56数据

Alright, let's break down how to pull data from a CY7C68013A (connected to a Xilinx Spartan-6 FPGA) using LabVIEW. I've tackled this setup a few times, so here's a step-by-step guide that should get you up and running:

First, make sure you have all the tools and hardware ready:

• CY7C68013A-based development board (or a custom peripheral with this chip)
• Xilinx Spartan-6 FPGA development board
• LabVIEW 2018 or newer (with NI-VISA and NI-USB Drivers installed)
• Cypress EZ-USB FX2 SDK (for writing firmware to the CY7C68013A)
• Xilinx ISE or Vivado (for programming the Spartan-6 FPGA logic)

The CY7C68013A needs custom firmware to bridge the FPGA and USB host (your PC running LabVIEW). Here's what to do:

• Open the Cypress FX2 SDK and create a new project. Choose the Slave FIFO mode—this is the most efficient way to transfer high-speed data between the FPGA and FX2.
• Configure USB endpoints: Use EP6 as the IN endpoint (sends data from FX2 to PC) and set it to Bulk Transfer mode. Match the endpoint buffer size to your FPGA's FIFO depth (512 bytes is a common starting point).
• Write core firmware logic:
  • Use SyncSlaveFifo() to synchronize FIFO read/write operations between the FPGA and FX2.
  • Implement logic to read data from the FPGA-connected FIFO and push it to the USB endpoint with USB_Write().
• Flash the firmware to the CY7C68013A using Cypress's Control Center tool—verify the chip is recognized by your PC afterward.

Your FPGA needs to feed data into the FX2's Slave FIFO. Follow these steps:

• Write Verilog/VHDL code to generate or acquire your target data (e.g., sensor readings, test patterns).
• Connect the FPGA's FIFO interface to the CY7C68013A's Slave FIFO pins:
  • Data bus: FIFOAD[15:0]
  • Control signals: SLWR (write enable), SLRD (read enable), SLOE (output enable), FLAGB (FIFO full flag), FLAGA (FIFO empty flag)
• Simulate and synthesize the FPGA logic, then program the Spartan-6. Use a logic analyzer to confirm data is being written to the FIFO correctly.

Now let's get LabVIEW talking to the setup. You have two reliable options:

4.1 Using NI-VISA (Recommended) #

NI-VISA is robust and widely supported. Here's the workflow:

1. Open LabVIEW and navigate to Instrument I/O > VISA in the Functions palette.
2. Use VISA Find Resources to locate your CY7C68013A device. The resource string will look like USB::VID_04B4::PID_XXXX::XXXX::INSTR (replace PID_XXXX with the value you set in your firmware).
3. Use VISA Open to establish a session with the device.
4. Use VISA Read to pull data from the IN endpoint (EP6). Make sure the "Number of bytes to read" matches your endpoint buffer size.
5. Convert the raw binary data to your desired format (e.g., integers, floats) using the Unflatten from String function—map the data type to what your FPGA is sending.
6. Always use VISA Close at the end of your program to release the device resource.

4.2 Using Cypress LabVIEW Driver #

If you have the Cypress-provided LabVIEW driver (included in the FX2 SDK), you can use their pre-built VIs for faster setup:

• Use EZ-USB Initialize.vi to connect to the device.
• Use EZ-USB Read.vi to fetch data from the IN endpoint.
• This skips low-level VISA configuration but may have less flexibility than the NI-VISA approach.

If you hit snags, try these fixes:

• Firmware first: Use Cypress Control Center to test if the FX2 can send data. If Control Center works, the issue is likely in LabVIEW or FPGA logic.
• Check FPGA-FX2 wiring: Use a logic analyzer to verify SLRD is triggered when FLAGB (FIFO full) is active—this confirms the FX2 is reading data from the FPGA.
• LabVIEW debugging: Enable VISA logging via Tools > Options > VISA > Debugging to trace communication errors. Use VISA Property Node to check device status.
• Timing matching: Ensure the FPGA writes data to the FIFO at a rate the FX2 can handle to avoid overflow or empty reads.

内容的提问来源于stack exchange，提问作者jack abraham