x86 CPU如何根据硬件中断确定执行哪个ISR？映射机制问询

Great question—let’s walk through how this works in x86 systems, step by step.

1. CPU如何确定要执行的ISR？ #

Here’s the play-by-play when a hardware device triggers an interrupt (like a keyboard press or disk I/O finishing up):

• The device sends an interrupt signal to the system’s interrupt controller (either the older PIC, Programmable Interrupt Controller, or the modern APIC, Advanced Programmable Interrupt Controller).
• The controller checks which interrupt has higher priority, resolves any conflicts, and sends a specific interrupt number over to the CPU.
• The CPU hits pause on its current instruction, saves its current state (registers, where it was in the code, etc.) to the stack, and temporarily disables other interrupts to avoid chaos.
• Using that interrupt number as an index, the CPU looks up a pre-built table in memory to find the entry address of the matching Interrupt Service Routine (ISR).
• It jumps to that address and runs the ISR. Once the ISR is done, the CPU pulls the saved state back from the stack and picks up where it left off.

2. 硬件中断号与ISR的映射存在吗？这个映射叫什么？ #

Absolutely—this mapping is the backbone of x86 interrupt handling, and it comes in two flavors depending on what mode the CPU is running in:

• Real Mode (used by BIOS and legacy systems): The mapping lives in the Interrupt Vector Table (IVT). This table is fixed at memory addresses 0x00000 to 0x003FF, with 256 total entries (one for each interrupt number 0–255). Each entry is 4 bytes: 2 bytes for the segment address, plus 2 bytes for the offset within that segment, pointing straight to the ISR.
• Protected Mode/Long Mode (used by all modern OSes like Linux, Windows, macOS): The mapping is stored in the Interrupt Descriptor Table (IDT). Unlike the IVT, the IDT can be anywhere in memory—its location and size are stored in the CPU’s IDTR register. Each entry (called a gate descriptor) is 8 bytes (Protected Mode) or 16 bytes (Long Mode), and it doesn’t just hold the ISR’s address—it also includes segment info and security permissions to keep things safe.

3. 这个映射表由谁或什么加载至内存？ #

Who’s in charge depends on what phase the system is in:

• Real Mode (BIOS startup): The BIOS sets up the initial IVT, filling entries for basic hardware interrupts (like keyboard, disk, or system timer) with its own simple ISRs. These default handlers are pretty barebones—they just handle basic device communication and often pass control back to the BIOS.
• Protected/Long Mode (OS running): The operating system takes full control here. First, it configures the IDTR register to point to a brand-new, OS-managed IDT in memory. Then, it replaces the BIOS’s default entries with its own custom ISRs—these are way more advanced, handling device drivers, switching between processes, and blocking unwanted interrupts. For example, Linux does this in the early boot setup_idt function, while Windows uses similar setup routines when the kernel starts up.

One quick side note: Older PIC controllers map hardware IRQs (Interrupt Requests) to interrupt numbers 0x08–0x0F and 0x70–0x77, which overlap with CPU exception codes (like division errors or page faults). Modern OSes always remap these IRQs to unused interrupt numbers (usually 0x20–0x2F) to avoid conflicts—this is all part of getting the IDT/IVT set up correctly.

内容的提问来源于stack exchange，提问作者thirstForKnowledge