关于Yosys的Verilog/SystemVerilog支持范围及相关问题的问询

Let's tackle each of your technical questions clearly, drawing on Yosys's official docs and project history:

1. Are there concise specifications or guides for Yosys's HDL support? #

Absolutely. The go-to resource is the official Yosys manual (which you're already referencing), but there are more accessible options too:

• Run help read or help read_verilog directly in the Yosys shell—this gives a quick, concise breakdown of command flags and supported features.
• The Yosys project maintains a feature support matrix in its repository documentation that explicitly lists which Verilog/SystemVerilog constructs are supported natively vs. via Verific.
• For practical use cases, you can also check the project's example designs and test suites, which demonstrate supported features in action.

2. What specific Verilog and SystemVerilog features does Yosys support? #

Native Yosys (without Verific) #

• Verilog: Supports nearly all synthesizable Verilog-2001/2005 constructs, including modules, ports, wires/regs, always blocks, case statements, parameterized modules, generate blocks, and standard primitives.
• SystemVerilog: Only a subset via the read_verilog -sv flag. Supported features include logic type, always_comb/always_ff/always_latch blocks, basic enums, limited structs, and simple packages. Most advanced SystemVerilog features (like interfaces with complex logic, cross-module references, or advanced data types) aren't supported natively.

With Verific Integration #

When using the read command with -sv2005/-sv2009/-sv2012 flags, Yosys leverages Verific to support full SystemVerilog compliance (matching the specified standard version) and complete Verilog support, including constructs that native Yosys can't handle.

3. What is Verific? #

Verific is a commercial, industry-standard HDL parsing and elaboration library. It's designed to fully implement all Verilog and SystemVerilog standards (including newer versions like SV-2017) with robust handling of complex edge cases. Yosys integrates with Verific as an optional plugin—this integration lets Yosys parse and elaborate sophisticated SystemVerilog designs that would fail with the native parser, making it suitable for larger, more complex projects.

4. Which parts of Verilog 2005 does Yosys NOT support (circa 2015)? #

From Clifford Wolf's 2015 talk and the corresponding documentation at the time, the main gaps in Verilog-2005 support were:

• Nested generate blocks with complex conditional logic that couldn't be fully elaborated
• A small set of simulation-only system tasks/functions (obscure $-prefixed operations that aren't used in synthesizable code)
• Non-synthesizable constructs like fork/join blocks
• Edge cases in parameterization semantics that rarely come up in real-world designs
• A few minor inconsistencies in procedural block behavior for very specific code patterns

5. How has Yosys's HDL support changed since late 2015? #

Since that 2015 lecture, Yosys has made massive strides in HDL support:

• Verilog 2005: The remaining minor gaps have mostly been fixed—native support is now effectively complete for all synthesizable Verilog-2005 constructs, with only niche non-synthesizable features still unsupported.
• SystemVerilog: Native support (via read_verilog -sv) has expanded significantly, adding better support for enums, structs, interfaces, and more of the SystemVerilog-2012 standard.
• Newer Standards: Partial support for Verilog-2017 has been added, focusing on synthesizable features.
• Verific Integration: The integration has been improved to support newer SystemVerilog versions (like SV-2017) and offer better error reporting and elaboration for complex designs.
• Robustness: Overall parsing and elaboration is more reliable, with better handling of edge cases and clearer error messages to help debug issues.

内容的提问来源于stack exchange，提问作者Øyvind Teig