Vivado 2020.2仿真中VHDL record字段未更新问题咨询

我最早在相关技术讨论中注意到该类问题，目前已整理出最小可复现用例（MCVE）如下：

DUT代码 #

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.top_pkg.all;

entity top is
  Port ( 
      clk : in std_logic;
      ce : in std_logic;
      input_custom_arr : in custom_record_array(4 downto 0);
      info : in custom_record;
      ctrl : in custom_record;
      output_custom_arr : out custom_record_array(4 downto 0)
  );
end top;

architecture Behavioral of top is

begin
    process(clk)
    begin
      if(ce = '1' and rising_edge(clk)) then
        output_custom_arr <= func_manipulate_custom_record_array(input_custom_arr, info, ctrl);
      end if;
    end process;
end Behavioral;

包含自定义函数和类型的包代码 #

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

package top_pkg is
    type custom_record is record
        data_1 : std_logic_vector(3 downto 0);
        data_2 : std_logic_vector(3 downto 0); 
        sync   : std_logic;   
        enable : std_logic;
    end record;

    type custom_record_array is ARRAY (INTEGER RANGE <>) of custom_record;

    FUNCTION func_manipulate_custom_record_array(dp : custom_record_array; info, ctrl : custom_record) RETURN custom_record_array;
end package;

package body top_pkg is

    FUNCTION func_manipulate_custom_record_array(dp : custom_record_array; info, ctrl : custom_record) RETURN custom_record_array is
        VARIABLE v_dp : custom_record_array(dp'RANGE) := dp;
        begin
            for I IN dp'RANGE LOOP
                v_dp(I).sync := info.sync;
                v_dp(I).enable := ctrl.enable;
            end loop;
        return v_dp;
        END func_manipulate_custom_record_array;
end package body;

仿真测试平台代码 #

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.top_pkg.all;

entity tb_top is
end tb_top;

architecture Behavioral of tb_top is
constant half_period : time := 10ns;
constant num_of_clocks : integer := 10;

signal input_custom_arr : custom_record_array(4 downto 0);
signal output_custom_arr : custom_record_array(4 downto 0);
signal info : custom_record := ((others=>'0'),(others=>'0'),'1','0');
signal ctrl : custom_record := ((others=>'0'),(others=>'0'),'0','1');
signal clk : std_logic := '0';
signal ce : std_logic := '0';
signal i : integer := 0;

begin
    -- 连续时钟生成
    process 
    begin
        clk <= '0';
        wait for half_period;
        clk <= '1';
        wait for half_period;

        if (i = num_of_clocks) then
            wait;
        elsif (i < 5) then
            input_custom_arr(i).data_1 <= std_logic_vector(TO_SIGNED(i,4));
            input_custom_arr(i).data_2 <= std_logic_vector(TO_SIGNED(4-i,4));
            i <= i + 1;
        elsif ( i = 5) then
            ce <= '1';
            i <= i + 1;
        else
            i <= i + 1;
        end if;
    end process;

    -- 例化待测设计
    u_dut : entity work.top
    port map(
        clk => clk,
        ce => ce,
        input_custom_arr => input_custom_arr,
        output_custom_arr => output_custom_arr,
        info => info,
        ctrl => ctrl
    );
end Behavioral;

问题现象 #

仿真运行后，第7个时钟周期可观测到output_custom_arr数组的sync、enable字段未按照函数逻辑完成更新。按照测试平台的配置逻辑，预期output_custom_arr中所有元素的sync和enable字段都应为'1'。

该问题和此前记录的「未修改字段被篡改」的record相关仿真问题不同，若代码本身不存在逻辑错误，是否可以证实Vivado（至少Windows 10环境下的2020.2版本）确实存在record类型相关的仿真异常？

内容的提问来源于stack exchange，提问作者Fo0ty