Verilog索引转值模块运行报错：=附近语法错误，期待.或(，如何解决

错误原因 #

• 连续赋值语句缺少assign关键字：Verilog中对wire型变量的连续赋值必须以assign开头，你代码中直接写oV = sequence[iState];不符合语法规范，这是触发10170错误的直接原因。
• 输入端口iState位宽不足：你定义的sequence数组共有15个元素，索引范围为0~14，至少需要4位位宽才能覆盖所有索引，当前定义的1位iState只能访问索引0和1，即使修复语法问题也无法实现预期功能。

修复后的完整代码 #

module StateToCountSequence(iState, oV);
    //declare the input and output 
    input [3:0] iState;
    output [3:0] oV;
  
    //declare any internal wire and reg types here.
    reg [3:0] sequence[14:0];
    
    initial begin
        sequence[0] = 4'd3;
        sequence[1] = 4'd2;
        sequence[2] = 4'd4;
        sequence[3] = 4'd9;
        sequence[4] = 4'd9;
        sequence[5] = 4'd0;
        sequence[6] = 4'd7;
        sequence[7] = 4'd1;
        sequence[8] = 4'd1;
        sequence[9] = 4'd5;
        sequence[10] = 4'd1;
        sequence[11] = 4'd7;
        sequence[12] = 4'd0;
        sequence[13] = 4'd8;
        sequence[14] = 4'd9;
    end

    assign oV = sequence[iState];
endmodule

补充说明 #

如果需要代码可综合，部分FPGA器件支持用initial块初始化寄存器数组，若器件不支持，可以将sequence改为用localparam定义的参数数组，功能完全一致。

内容的提问来源于stack exchange，提问作者kene02