7段数码管加法实现VHDL代码ADD case分支未全覆盖报错求助

问题背景 #

我正在实现7段数码管的加法功能：两路输入数值分别在各自对应的数码管显示，相加结果输出到第三、第四个数码管显示，结果为两位数，取值范围0~14。当前运行代码时抛出错误，提示ADD对应的case语句需要覆盖所有实例，无法确定修正方向，相关原始代码如下：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY  Midterm2_Q2_4369 IS
PORT (
SW: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
SW0: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
ADD: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
Y0: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
Y1: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
Y2: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END Midterm2_Q2_4369;
ARCHITECTURE MUX8 OF Midterm2_Q2_4369 IS 
BEGIN
PROCESS (SW,SW0,ADD)
BEGIN
CASE SW IS
WHEN "000" => Y <= "0000001";
WHEN "001" => Y <= "1001111";
WHEN "010" => Y <= "0010010";
WHEN "011" => Y <= "0000110";
WHEN "100" => Y <= "1001100";
WHEN "101" => Y <= "0100100";
WHEN "110" => Y <= "0100000";
WHEN "111" => Y <= "0001111";
END CASE;
CASE SW0 IS
WHEN "000" => Y0 <= "0000001";
WHEN "001" => Y0 <= "1001111";
WHEN "010" => Y0 <= "0010010";
WHEN "011" => Y0 <= "0000110";
WHEN "100" => Y0 <= "1001100";
WHEN "101" => Y0 <= "0100100";
WHEN "110" => Y0 <= "0100000";
WHEN "111" => Y0 <= "0001111";
END CASE;
CASE ADD IS
WHEN "0000000" => Y1 <= "0000001"; --0
WHEN "0000001" => Y1 <= "1001111"; --1
WHEN "0000010" => Y1 <= "0010010"; --2
WHEN "0000011" => Y1 <= "0000110"; --3
WHEN "0000100" => Y1 <= "1001100"; --4
WHEN "0000101" => Y1 <= "0100100"; --5
WHEN "0000110" => Y1 <= "0100000"; --6
WHEN "0000111" => Y1 <= "0001111"; --7
WHEN "0001111" => Y1 <= "0000000"; --8
WHEN "0010111" => Y1 <= "0000100"; --9
     --8421421
WHEN "0011111" => Y2 <= "1001111"; --(1)0
WHEN "0100111" => Y2 <= "1001111"; --(1)1
WHEN "0101111" => Y2 <= "1001111"; --(1)2
WHEN "0110111" => Y2 <= "1001111"; --(1)3
WHEN "0111111" => Y2 <= "1001111"; --(1)4--
WHEN "1000111" => Y2 <= "1001111"; --(1)5
WHEN "1001111" => Y2 <= "1001111"; --(1)6
WHEN "1010111" => Y2 <= "1001111"; --(1)7--
WHEN "1011111" => Y2 <= "1001111"; --(1)8
WHEN "1100111" => Y2 <= "1001111"; --(1)9
END CASE;
END PROCESS;
END MUX8;

错误原因梳理 #

• ADD是7位的STD_LOGIC_VECTOR类型，总共有128种可能的取值，你当前的CASE语句仅列了20种取值，没有覆盖所有可能，VHDL的CASE语句要求必须穷尽所有输入分支，否则会直接编译报错。
• 逻辑设计存在缺陷：ADD不应该设为7位输入，正确逻辑是先对两路3位输入（SW、SW0取值范围均为0_{7）做加法得到4位的和（取值范围0}14），再把和拆分为十位和个位，分别转7段编码输出，你现在直接把7位ADD作为输入写分支，逻辑完全偏离需求。
• 现有ADD分支的赋值逻辑混乱，每个分支仅给Y1或者Y2其中一个输出赋值，另一个输出会生成不必要的锁存，不符合组合逻辑设计规范。

修正后的完整代码 #

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; -- 引入数值运算库实现加法
ENTITY  Midterm2_Q2_4369 IS
PORT (
    SW: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    SW0: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    Y: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- 第一路输入对应数码管
    Y0: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- 第二路输入对应数码管
    Y1: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- 结果个位数码管
    Y2: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)  -- 结果十位数码管
);
END Midterm2_Q2_4369;
ARCHITECTURE MUX8 OF Midterm2_Q2_4369 IS 
    -- 内部信号：加法运算结果，3位+3位最大为14，用4位存储足够
    SIGNAL sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
    -- 内部信号：和的个位、十位
    SIGNAL sum_unit : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL sum_ten : STD_LOGIC_VECTOR(3 DOWNTO 0);
    
    -- 自定义转换函数：4位BCD值转7段数码管编码，减少重复代码
    FUNCTION bcd_to_7seg(bcd : STD_LOGIC_VECTOR(3 DOWNTO 0)) RETURN STD_LOGIC_VECTOR IS
    BEGIN
        CASE bcd IS
            WHEN "0000" => RETURN "0000001"; -- 0
            WHEN "0001" => RETURN "1001111"; -- 1
            WHEN "0010" => RETURN "0010010"; -- 2
            WHEN "0011" => RETURN "0000110"; -- 3
            WHEN "0100" => RETURN "1001100"; -- 4
            WHEN "0101" => RETURN "0100100"; -- 5
            WHEN "0110" => RETURN "0100000"; -- 6
            WHEN "0111" => RETURN "0001111"; -- 7
            WHEN "1000" => RETURN "0000000"; -- 8
            WHEN "1001" => RETURN "0000100"; -- 9
            WHEN OTHERS => RETURN "1111111"; -- 非法值灭灯，覆盖所有剩余分支
        END CASE;
    END FUNCTION;
BEGIN
    -- 第一步：计算两路输入的和
    sum <= STD_LOGIC_VECTOR(UNSIGNED('0' & SW) + UNSIGNED('0' & SW0));
    
    -- 第二步：拆分和的十位和个位，结果最大为14，十位只有0和1两种取值
    sum_ten <= "0001" WHEN UNSIGNED(sum) >= 10 ELSE "0000";
    sum_unit <= STD_LOGIC_VECTOR(UNSIGNED(sum) - 10) WHEN UNSIGNED(sum) >= 10 ELSE sum;
    
    -- 第三步：所有数值转7段编码输出
    Y <= bcd_to_7seg('0' & SW);
    Y0 <= bcd_to_7seg('0' & SW0);
    Y1 <= bcd_to_7seg(sum_unit);
    Y2 <= bcd_to_7seg(sum_ten);
END MUX8;

关键修改说明 #

• 新增WHEN OTHERS分支覆盖CASE语句所有可能的取值，直接解决原代码的编译报错问题。
• 引入IEEE.NUMERIC_STD库实现无符号数加法，不需要手动写加法逻辑，降低出错概率。
• 拆分加法运算、位拆分、7段编码三个逻辑步骤，代码结构清晰，不会生成不必要的锁存。
• 复用7段编码转换函数，减少重复代码，后续调整数码管编码仅需要修改函数内的对应分支即可。

内容的提问来源于stack exchange，提问作者Kyle Gerik