ESP32使用JTAG烧录在Programming Finished后出现验证错误问题

故障现象 #

代码可正常构建，此前也能正常烧录到自制ESP32开发板上使用，烧录功能突然失效后，已通过更换不同PCB板、数据线排查解决烧录通路问题，当前烧录流程可正常执行到Programming Finished阶段，但启动验证后直接报错。

完整终端日志 #

Processing esp32dev (platform: espressif32; board: esp32dev; framework: espidf)
-----------------------------------------------------------------------------------------------------------
Verbose mode can be enabled via `-v, --verbose` option
CONFIGURATION: https://docs.platformio.org/page/boards/espressif32/esp32dev.html
PLATFORM: Espressif 32 (3.4.0) > Espressif ESP32 Dev Module
HARDWARE: ESP32 240MHz, 320KB RAM, 4MB Flash
DEBUG: Current (esp-prog) External (esp-prog, iot-bus-jtag, jlink, minimodule, olimex-arm-usb-ocd, olimex-arm-usb-ocd-h, olimex-arm-usb-tiny-h, olimex-jtag-tiny, tumpa)
PACKAGES: 
 - framework-espidf 3.40301.0 (4.3.1) 
 - tool-cmake 3.16.4 
 - tool-esptoolpy 1.30100.210531 (3.1.0) 
 - tool-mkspiffs 2.230.0 (2.30) 
 - tool-ninja 1.9.0 
 - tool-openocd-esp32 2.1000.20210721 (10.0) 
 - toolchain-esp32ulp 1.22851.191205 (2.28.51) 
 - toolchain-riscv32-esp 8.4.0+2021r1 
 - toolchain-xtensa-esp32 8.4.0+2021r1 
 - toolchain-xtensa-esp32s2 8.4.0+2021r1
Reading CMake configuration...
LDF: Library Dependency Finder -> 
LDF Modes: Finder ~ chain, Compatibility ~ soft
Found 0 compatible libraries
Scanning dependencies...
No dependencies
Building in debug mode
Retrieving maximum program size .pio/build/esp32dev/firmware.elf
Checking size .pio/build/esp32dev/firmware.elf
Advanced Memory Usage is available via "PlatformIO Home > Project Inspect"
RAM:   [=         ]  10.1% (used 32992 bytes from 327680 bytes)
Flash: [========  ]  75.7% (used 794197 bytes from 1048576 bytes)
Configuring upload protocol...
AVAILABLE: esp-prog, espota, esptool, iot-bus-jtag, jlink, minimodule, olimex-arm-usb-ocd, olimex-arm-usb-ocd-h, olimex-arm-usb-tiny-h, olimex-jtag-tiny, tumpa
CURRENT: upload_protocol = esp-prog
Uploading .pio/build/esp32dev/firmware.bin
Open On-Chip Debugger  v0.10.0-esp32-20210721 (2021-07-21-13:34)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
debug_level: 1

adapter speed: 20000 kHz

WARNING: boards/esp-wroom-32.cfg is deprecated, and may be removed in a future release.
adapter speed: 2000 kHz

** Programming Started **
** Programming Finished **
** Verify Started **
Error: **** Verification failure! ****
Error: target_hash cbc6a9...992065
Error: file_hash: 773d62...93803f
embedded:startup.tcl:449: Error: ** Verify Failed **
in procedure 'program_esp' 
in procedure 'program_error' called at file "/Users/USER/.platformio/packages/tool-openocd-esp32/share/openocd/scripts/target/esp_common.cfg", line 135
at file "embedded:startup.tcl", line 449
*** [upload] Error 1

排查修复方案 #

• 降低JTAG烧录速率：在platformio.ini配置文件中添加upload_speed = 1000，将烧录速率降到1000kHz后重试，自制PCB布线信号质量不足时，高频烧录容易出现写入数据错误但不触发烧录报错的情况。
• 核对Flash参数匹配：确认开发板实际搭载的Flash容量、SPI模式、工作频率与配置一致，在platformio.ini中添加对应配置，示例如下：

board_build.flash_size = 4MB
board_build.flash_mode = dio
board_build.flash_freq = 40m

参数根据实际硬件调整即可，参数不匹配会导致写入地址偏移，引发校验失败。

• 全片擦除Flash后再烧录：先执行Flash全擦除操作，可通过esptool执行命令esptool.py erase_flash，也可直接在PlatformIO的任务列表中选择「Erase Flash」执行，擦除完成后再重新烧录固件，排除残留旧数据干扰。
• 检查硬件接线与供电：确认ESP-PROG与开发板的JTAG接线（尤其是SRST、TRST引脚）接触良好，烧录时断开开发板其他高功耗外设，保证3.3V供电稳定，供电纹波过大也会导致Flash写入数据错误。
• 替换废弃配置：日志提示boards/esp-wroom-32.cfg已废弃，在platformio.ini中显式指定debug_tool = esp-prog，使用官方推荐的目标配置，避免废弃配置引发的读写逻辑异常。

内容的提问来源于stack exchange，提问作者Norbert Buchmuller