Verilog三维数组打包解包宏及加法模块编译错误求助

Hey there! Let's work through these compilation errors step by step. I can see a few key issues in your macros and module code that are causing the syntax problems:

Key Issues Identified #

• Invalid Nested generate Blocks: Your macros have nested generate statements, which aren't allowed in Verilog. A single generate block can contain multiple loops without needing nested generate/endgenerate pairs.
• Bit-Select Parenthesis Error: There's a misplaced closing parenthesis in your bit-slice expressions (e.g., (PK_WIDTH)-1):0 should be (PK_WIDTH-1):0).
• Assigning to reg Variables: You're using assign statements (from the macros) to drive reg-type signals (g_unpack, e_unpack). assign only works with wire types.
• Missing Semicolon: The line integer i_d, i_h, i_w is missing a trailing semicolon, breaking the syntax for the following always block.
• Loop Bound Mismatch: Your addition loops use d (depth) as the bound for height and width iterations, which is incorrect—should use h for height and w for width.

Corrected Code #

Fixed Pack/Unpack Macros #

`define PACK_3D(PK_WIDTH, PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST) \
genvar pk_idh; \
genvar pk_idd; \
generate \
    for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin : depth_loop_pack \
        for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin : height_loop_pack \
            assign PK_DEST[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1) : pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)] = PK_SRC[pk_idd][pk_idh][PK_WIDTH-1:0]; \
        end \
    end \
endgenerate

`define UNPACK_3D(PK_WIDTH, PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST) \
genvar pk_idh; \
genvar pk_idd; \
generate \
    for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin : depth_loop_unpack \
        for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin : height_loop_unpack \
            assign PK_DEST[pk_idd][pk_idh][PK_WIDTH-1:0] = PK_SRC[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1) : pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)]; \
        end \
    end \
endgenerate

Corrected Matrix Addition Module #

module add(clk, rst, g_input, e_input, o);
input clk, rst;
localparam num=4;
localparam h = 3;
localparam w = 3;
localparam d = 2;

input [2*num*h*w*d-1:0] g_input;
input [2*num*h*w*d-1:0] e_input;
output reg [2*num*h*w*d-1:0] o;

// Change reg to wire since we're using assign from macros
wire [2*num -1: 0] g_unpack[d-1:0][h-1:0][w-1:0];
wire [2*num -1: 0] e_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] o_unpack[d-1:0][h-1:0][w-1:0];

`UNPACK_3D(w, h, d, g_input, g_unpack);
`UNPACK_3D(w, h, d, e_input, e_unpack);

// Added missing semicolon
integer i_d, i_h, i_w;

always@* // always combinational block
begin
    for (i_d = 0; i_d < d; i_d = i_d+1) begin
        // Fixed loop bound from d to h
        for (i_h = 0; i_h < h; i_h = i_h+1) begin
            // Fixed loop bound from d to w
            for (i_w = 0; i_w < w; i_w = i_w+1) begin
                o_unpack[i_d][i_h][i_w] = g_unpack[i_d][i_h][i_w] + e_unpack[i_d][i_h][i_w];
            end
        end
    end
end

// Note: PACK_3D expects PK_DEST to be a wire, but o is reg. We'll use an intermediate wire
wire [2*num*h*w*d-1:0] o_temp;
`PACK_3D(w, h, d, o_unpack, o_temp);

// Assign temp wire to output reg (since o is reg)
always@(posedge clk or posedge rst) begin
    if(rst) begin
        o <= '0;
    end else begin
        o <= o_temp;
    end
end

endmodule

Additional Notes #

• I added named blocks to the generate loops (depth_loop_pack, etc.)—this is optional but helps with debugging and avoids potential naming conflicts.
• The output o is a reg, so we can't directly use PACK_3D to assign to it. Instead, we pack to an intermediate wire and then assign that to o in a clocked always block (which also properly handles the reset signal, since your module has a rst input).

内容的提问来源于stack exchange，提问作者Yash Kant