ModelSim中Verilog代码vlog-13069语法错误排查与修复求助

错误根源 #

编译器报错指向第60行，但实际语法错误出现在**register_update always块中的Data <= unsigned(IO);语句**：

• Verilog中不存在无美元符号的unsigned函数，正确的系统类型转换函数是$unsigned，缺少$会导致编译器解析逻辑混乱，进而将错误提示偏移到后续代码行。

修复步骤 #

1. 修正类型转换函数
   将错误语句改为：

Data <= $unsigned(IO);

2. 初始化未赋值寄存器
   Address和Data寄存器在initial块中未初始化，仿真时会出现不确定值（x），需添加初始化代码：

initial begin
    inc_adrs = 1'b0; 
    inc_data = 1'b0; 
    ld_data = 1'b0; 
    en_data = 1'b0; 
    clk = 1'b0;
    Cs_b = 1'b0; 
    Oe_b = 1'b0; 
    done = 1'b0; 
    We_b = 1'b1; 
    Address = 8'b0; // 初始化地址寄存器
    Data = 8'b0;    // 初始化数据寄存器
end

3. 可选优化：规范case语句常量
   state是2位寄存器，建议为case中的常量显式指定位宽，避免隐式类型转换：

case(state)
    2'd0:  begin
        Oe_b = 1'b0; 
        ld_data = 1'b1; 
        next_state = 2'd1;
    end
    2'd1:  begin
        inc_data = 1'b1; 
        next_state = 2'd2;
    end
    2'd2:  begin
        We_b = 1'b0; 
        en_data = 1'b1; 
        inc_adrs = 1'b1; 
        next_state = 2'd3;
    end
    2'd3:  begin
        if (Address == 8'b00100000) begin
            done = 1'b1; 
            next_state = 2'd3;
        end 
        else begin
            next_state = 2'd0;
        end
    end
endcase

修复后的完整代码 #

module RAM6116_system ();
reg[1:0] state; 
reg[1:0] next_state; 
reg inc_adrs; 
reg inc_data; 
reg ld_data; 
reg en_data; 
reg Cs_b; 
reg clk; 
reg Oe_b; 
reg done; 
reg We_b; 
reg[7:0] Data; 
reg[7:0] Address; 
wire[7:0] IO;

initial begin
    inc_adrs = 1'b0; 
    inc_data = 1'b0; 
    ld_data = 1'b0; 
    en_data = 1'b0; 
    clk = 1'b0;
    Cs_b = 1'b0; 
    Oe_b = 1'b0; 
    done = 1'b0; 
    We_b = 1'b1; 
    Address = 8'b0;
    Data = 8'b0;
end

RAM6116 RAM1 (Cs_b, We_b, Oe_b, Address, IO);

always @(state or Address) 
begin : control
    ld_data = 1'b0; 
    inc_data = 1'b0; 
    inc_adrs = 1'b0; 
    en_data = 1'b0; 
    done = 1'b0;
    We_b = 1'b1; 
    Cs_b = 1'b0; 
    Oe_b = 1'b1;

    case(state)
        2'd0:  begin
            Oe_b = 1'b0; 
            ld_data = 1'b1; 
            next_state = 2'd1;
        end
        2'd1:  begin
            inc_data = 1'b1; 
            next_state = 2'd2;
        end
        2'd2:  begin
            We_b = 1'b0; 
            en_data = 1'b1; 
            inc_adrs = 1'b1; 
            next_state = 2'd3;
        end
        2'd3:  begin // 原错误提示行，问题已修复
            if (Address == 8'b00100000) begin
                done = 1'b1; 
                next_state = 2'd3;
            end 
            else begin
                next_state = 2'd0;
            end
        end
    endcase
end

always @(posedge clk) 
begin : register_update
    state <= next_state; 
    if (inc_data == 1'b1) 
    begin
        Data <= Data + 1;
    end 
    if (ld_data == 1'b1) 
    begin
        Data <= $unsigned(IO);
    end
    if (inc_adrs == 1'b1)
    begin
        Address <= #1 Address + 1;
    end
end

always #100 clk = ~clk; 
assign IO = (en_data ==1'b1) ? Data : 8'bZZZZZZZZ;
endmodule

内容的提问来源于stack exchange，提问作者Queries17