SystemVerilog多维数组访问方法及mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask]语句解析

Hey there! Let's break down your SystemVerilog array questions clearly and step by step.

SystemVerilog supports multiple types of multi-dimensional arrays, and their access methods vary slightly. Here's a breakdown of the common types:

• Static multi-dimensional arrays: These are the most basic fixed-size arrays, where you specify all dimension sizes during declaration, for example:

  int my_array[2][3]; // A 2-row, 3-column integer array
  

  To access elements, use indices in left-to-right dimension order. For example, to get the element in the first row and second column:

  int val = my_array[0][1]; // Indices start at 0, consistent with most programming languages
  

• Dynamic multi-dimensional arrays: The size of these arrays can be allocated at runtime. Leave some or all dimensions empty when declaring, like:

  int dyn_array[][]; // A 2D dynamic array
  

  You need to allocate space before accessing elements, and the access method is identical to static arrays afterward:

  dyn_array = new[2];       // Allocate the first dimension (2 rows)
  dyn_array[0] = new[3];    // Allocate 3 columns for the first row
  int val = dyn_array[0][1];// Access the element
  

• Associative arrays: Used for storing data of uncertain size or sparse data, supporting non-integer types (such as strings, enums) as indices, for example:

  int assoc_array[string][int]; // First dimension uses string keys, second uses integer indices
  

  Access elements directly using the corresponding keys and indices:

  assoc_array["config"][5] = 100; // Assign a value
  int val = assoc_array["config"][5]; // Retrieve the value
  

• Mixed-type arrays: For example, a combination of static and dynamic like int mixed_array[2][];. When accessing, ensure the dynamic dimension is allocated first, then use indices in order.

This statement is a practical combination of multi-dimensional array access + continuous part-select in SystemVerilog. The core is understanding the special +: syntax:

Breakdown of each part: #

1. mem: This should be a 2D memory array, typically defined like reg [DATA_WIDTH-1:0] mem[ADDR_DEPTH-1:0]; — the first dimension is the address index (corresponding to addr_i), and each address corresponds to a wide-bit vector of DATA_WIDTH bits.
2. addr_i: Used to select the specific memory cell (the wide-bit data corresponding to an address).
3. i*DataBitsPerMask +: DataBitsPerMask: This is SystemVerilog's Indexed Part-Select syntax, which solves the problem that ordinary bit selection [high:low] cannot use variables as boundaries.

Deep dive into the +: syntax: #

The syntax format is: start_index +: width, with the following rules:

• Start at the position specified by start_index, and select width consecutive bits (or array elements) in the direction of higher indices/bit numbers.
• Note: width must be a constant, while start_index can be a variable — this is its biggest advantage over ordinary bit selection.

Practical example: #

Suppose DataBitsPerMask = 8 (select 8 bits each time) and DATA_WIDTH = 32 (each memory cell is 32 bits):

• When i=0, 0*8 +:8 is equivalent to [7:0], selecting the lower 8 bits of the address cell;
• When i=1, 1*8 +:8 is equivalent to [15:8], selecting the middle 8 bits;
• When i=2, 2*8 +:8 is equivalent to [23:16], selecting the next highest 8 bits;
• When i=3, 3*8 +:8 is equivalent to [31:24], selecting the upper 8 bits.

This writing style is not only concise but also allows you to traverse all segments by looping over i when you need to split wide-bit data into fixed-width chunks, making it very flexible.

As a side note, the corresponding -: syntax: start_index -: width selects width consecutive bits in the direction of lower indices/bit numbers starting from start_index. For example, 15 -:8 is also equivalent to [15:8], which gives the same result as 1*8 +:8 above, just with a different starting point description.

内容的提问来源于stack exchange，提问作者Zeeshan Rafique