如何实现4x1 MUX测试平台？现有测试代码仿真出现未定义错误

问题背景 #

用户编写了4x1 MUX的VHDL代码，并完成了部分测试平台，但行为仿真时出现未定义错误。

MUX核心代码 #

---------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------
ENTITY mux IS
    PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
         y: OUT STD_LOGIC);
END mux;
---------------------------------------
ARCHITECTURE pure_logic OF mux IS
BEGIN
    y <= (a AND NOT s1 AND NOT s0) OR
 (b AND NOT s1 AND s0) OR
 (c AND s1 AND NOT s0) OR
 (d AND s1 AND s0);
END pure_logic;
---------------------------------------

原始测试平台代码 #

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_tb is
--  Port ( );
end mux_tb;

architecture Behavioral of mux_tb is
    component mux
         PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
         y: OUT STD_LOGIC);
    end component;

    signal a : std_logic;
    signal b : std_logic;
    signal c : std_logic;
    signal d : std_logic;
    signal s0 : std_logic;
    signal s1 : std_logic;
    signal y : std_logic;
 
begin
    uut: mux port map (
        a => a,
        b => b,
        c => c,
        d => d,
        s0 => s0,
        s1 => s1,
        y => y
    );

    process
    begin
    s0 <= '0'; s1 <= '0';
    wait for 100 ns;
    s1 <= '0'; s0 <= '1';
    wait for 100ns;
    s1 <= '1'; s0 <= '0';
    wait for 100ns;
    s1 <= '1'; s0 <= '1';

    end process;
end Behavioral;

错误点解析 #

• 输入信号未初始化：测试平台中仅对选择信号s0、s1赋值，但a、b、c、d未设置任何初始值。在VHDL中，未赋值的std_logic信号默认值为'U'（未定义状态），代入MUX的逻辑表达式后，输出y必然会出现未定义错误。
• 测试进程无终止逻辑：当前进程在最后一次赋值后没有添加等待语句，会导致进程无限重复执行最后一行代码，部分仿真工具会因此报错或陷入死循环。
• 格式不统一（潜在问题）：wait for 100 ns;和wait for 100ns;的空格格式不一致，虽然多数工具兼容，但统一格式能避免不必要的语法识别问题。

修正后的测试平台代码 #

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_tb is
end mux_tb;

architecture Behavioral of mux_tb is
    component mux
         PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
                y: OUT STD_LOGIC);
    end component;

    signal a : std_logic := '1'; -- 初始化输入信号
    signal b : std_logic := '0';
    signal c : std_logic := '1';
    signal d : std_logic := '0';
    signal s0 : std_logic;
    signal s1 : std_logic;
    signal y : std_logic;
 
begin
    uut: mux port map (
        a => a,
        b => b,
        c => c,
        d => d,
        s0 => s0,
        s1 => s1,
        y => y
    );

    process
    begin
        s0 <= '0'; s1 <= '0';
        wait for 100 ns;
        s1 <= '0'; s0 <= '1';
        wait for 100 ns;
        s1 <= '1'; s0 <= '0';
        wait for 100 ns;
        s1 <= '1'; s0 <= '1';
        wait for 100 ns; -- 最后一次状态保持时间
        wait; -- 终止进程，避免无限循环
    end process;
end Behavioral;

内容的提问来源于stack exchange，提问作者Ngoloo