JK触发器计数器代码报错：非法引用net变量JA，求修复方案

Let's break down why you're hitting that vlog-2110 error and walk through how to fix it:

Root Cause #

In your Counter module, you incorrectly declared JA, KA, JB, KB, JC, KC as input ports. In Verilog, input ports default to wire (net) type, and you can't assign values to nets inside an always block—process blocks like always @(...) can only drive reg type variables. Your attempt to use non-blocking assignments (<=) on these net signals directly violates Verilog's syntax rules.

On top of that, these signals shouldn't be inputs at all! They're internal control signals your counter generates to drive the J/K pins of your JK_FF instances, not signals coming from outside the module.

Step-by-Step Fix #

1. Remove JA/KA/JB/KB/JC/KC from the Counter's input port list—they're internal to the module, not external inputs.
2. Declare JA/KA/JB/KB/JC/KC as reg variables inside the Counter module so you can assign them in the always block.
3. Clean up redundant reset logic—you don't need to re-assign A, B, C in the Counter's always block because the JK_FF modules already handle their own reset behavior.
4. Fix a critical JK flip-flop typo—your JK_FF has an incorrect behavior for the 2'b10 (J=1, K=0) case, which will break your counting sequence if left unaddressed.

Corrected Code #

First, here's the fixed JK_FF module (note the corrected 2'b10 case):

module JK_FF (Q, J, K, clk, rst);
output Q;
input J, K, clk, rst;
reg Q;

always @ (posedge clk or negedge rst) begin
    if(!rst) 
        Q <= 1'b0;
    else begin
        case ({J,K})
            2'b00: Q <= Q;       // Hold
            2'b01: Q <= 1'b0;     // Reset
            2'b10: Q <= 1'b1;     // Set (fixed from original 1'b0)
            2'b11: Q <= ~Q;       // Toggle
        endcase
    end
end
endmodule

And here's the fixed Counter module:

module Counter(A,B,C,clk,rst,in);
output A,B,C;
input clk,rst,in;

// Declare internal J/K control signals as reg
reg JA, KA, JB, KB, JC, KC;

// Instantiate JK flip-flops
JK_FF JKA(A,JA,KA,clk,rst);
JK_FF JKB(B,JB,KB,clk,rst);
JK_FF JKC(C,JC,KC,clk,rst);

always @ (posedge clk or negedge rst) begin
    if(!rst) begin
        // Reset internal control signals to avoid startup glitches
        JA <= 1'b0;
        KA <= 1'b0;
        JB <= 1'b0;
        KB <= 1'b0;
        JC <= 1'b0;
        KC <= 1'b0;
    end else if(in == 1'b1) begin
        // Assign J/K logic for your 0->1->2->3->4->0 mod-5 counter
        JA <= B & C; 
        KA <= 1'b1; 
        JB <= C; 
        KB <= C; 
        JC <= ~A; 
        KC <= 1'b1;
    end
end
endmodule

Quick Check #

After these fixes, your code will:

• No longer throw the net reference error
• Implement correct JK flip-flop behavior
• Generate the internal control signals properly to drive your desired count sequence

内容的提问来源于stack exchange，提问作者Newnew