SystemVerilog中always_comb无法推断纯组合逻辑问题求助

无法解决这个错误，卡在此问题上一段时间，陷入循环，不确定遗漏了什么。错误指向第一个if语句所在行。想要实现的是一个模式选择功能：mode=1时在FPGA上显示特定信息，mode=0时显示不同信息。

modesel模块代码 #

module modesel(input logic mode, clk, reset, 
                    input logic [6:0] LOAD,
                    input logic [7:0] pc, ac, state, mdr, opcode, value, address,
                    output logic [9:0] LEDR,
                    output logic [7:0] left, middle, right);
    
            up3(.clk(clk), .reset(reset), .store_mem(LOAD[0]), .fetch(LOAD[1]), .load_pc(LOAD[3]), .incr_pc(LOAD[2]), .load_iru(LOAD[5]), .load_irl(LOAD[4]), .load_ac(LOAD[6]), 
                      .pc(pc), .ac(ac), .state(state), .mdr(mdr), .opcode(opcode), .value(value), .address(address));
            
               always_comb
            
                if (mode==1) begin//mode1   
                    LEDR[6:0] = LOAD[6:0];
                    LEDR[8:7] = 0;
                    LEDR[9] = 1;
                    left = pc;
                    middle = address;
                    right = mdr;
                    
                end
            
                else if(mode==0) begin//mode0
                    case(state)
                        8'h00: LEDR[7:0] = 8'b0000_0000;
                        8'h01: LEDR[7:0] = 8'b0000_0001;
                        8'h02: LEDR[7:0] = 8'b0000_0010;
                        8'h03: LEDR[7:0] = 8'b0000_0100;
                        8'h04: LEDR[7:0] = 8'b0000_1000;
                        8'h05: LEDR[7:0] = 8'b0001_0000;
                        8'h06: LEDR[7:0] = 8'b0010_0000;
                        8'h07: LEDR[7:0] = 8'b0100_0000;
                        8'h08: LEDR[7:0] = 8'b1000_0010;
                        default: LEDR[7:0] = 8'b0000_0000;
                    endcase
                    LEDR[9:8] = 0;
                    left = opcode;
                    middle = value;
                    right = ac;
                    
                end
                
endmodule

up3模块端口定义 #

module up3(input logic clk, reset, 
            output logic store_mem, fetch, load_pc, incr_pc, load_iru, load_irl, load_ac,
            output logic [7:0] pc, ac, state, mdr, opcode, value, address);

错误信息 #

Error (10166): SystemVerilog RTL Coding error at modesel.sv(16): always_comb construct does not infer purely combinational logic.

测试台代码（用于DE0CV FPGA板） #

module up3tb(input logic [3:0] KEY,
             output logic [9:0] LEDR,
             output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5);    

logic [6:0] LOAD;
logic [7:0] PC, AC, STA, MDR, OPC, VAL, ADR, L, M, R;


 modesel test( .mode(KEY[3]), .clk(KEY[0]), .reset(KEY[1]), 
                    .LOAD(LOAD[6:0]),
                    .pc(PC), .ac(AC), .state(STA), .mdr(MDR), .opcode(OPC), .value(VAL), .address(ADR),
                    .LEDR(LEDR[9:0]),
                    .left(L), .middle(M), .right(R));
                    
                
            dual_seg7 L_out(.blank(0), .test(0), .data(L), .segments1(HEX5), .segments2(HEX4));//Left, PC or Opcode
            dual_seg7 M_out(.blank(0), .test(0), .data(M), .segments1(HEX3), .segments2(HEX2));//Middle, Address or Value
            dual_seg7 R_out(.blank(0), .test(0), .data(R), .segments1(HEX1), .segments2(HEX0));//RIght, AC or MDR
            
            
endmodule

尝试过在always_comb块外添加assign语句等方法，但出现更多错误，恳请帮助。

内容的提问来源于stack exchange，提问作者Adam Montano