VHDL WHEN ELSE语句报错排查及投票系统代码修正请求

Hey there! Let's walk through fixing your code—we'll tackle both the compilation errors and align the logic perfectly with your voting rules.

1. The Immediate Syntax Error (Why You're Seeing COMP96 Errors) #

The root cause of those compilation failures is on line 24 of your code: you used => instead of <= to assign the l3 signal. In VHDL:

• <= is the correct operator for assigning values to signals inside an architecture
• => is only used for port mappings, aggregate assignments, or linking elements in configurations

Swap that => for <=, and those syntax errors will vanish right away.

2. Fixing Logical Discrepancies #

Your original code also has a mismatch with your stated requirements:

• You included the all-0 input case (j1-j4 all '0') in l3's conditions, but your rule says only when exactly 1 input is '1' should l3='1'
• Your l1 and l2 logic works, but enumerating every possible input combination is tedious and hard to maintain

3. Simplified & Corrected Code #

A cleaner, more scalable approach is to count how many inputs are '1', then use that count to drive your outputs. This avoids listing every possible input combination and makes the logic easy to read.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; -- Needed for the count_ones function

ENTITY SistemaVotacion IS
PORT (
    j1, j2, j3, j4: IN std_logic;
    l1, l2, l3: OUT std_logic
);
END SistemaVotacion;

ARCHITECTURE SistemaArchitecture OF SistemaVotacion IS
    SIGNAL input_vector : std_logic_vector(3 DOWNTO 0);
    SIGNAL vote_count : integer RANGE 0 TO 4;
BEGIN
    -- Combine individual inputs into a single vector for easier counting
    input_vector <= j1 & j2 & j3 & j4;
    -- Tally up how many inputs are '1'
    vote_count <= count_ones(input_vector);

    -- Apply your voting rules directly from the count
    l1 <= '1' WHEN vote_count > 2 ELSE '0'; -- Triggers for 3 or 4 '1's
    l2 <= '1' WHEN vote_count = 2 ELSE '0';
    l3 <= '1' WHEN vote_count = 1 ELSE '0'; -- Only triggers for exactly 1 '1'
END SistemaArchitecture;

4. What We Improved #

• Syntax Fix: Replaced => with <= for the l3 signal assignment
• Logical Alignment: Removed the all-0 case from l3 to match your requirement of only 1 '1' triggering it
• Readability & Maintainability:
  • Used a vector to group inputs and the count_ones function to tally votes (no more manual enumeration of every input combo)
  • Conditional assignments directly mirror your rules, making the logic clear at a glance

5. If You Want to Stick to Only STD_LOGIC_1164 #

If you prefer not to use the NUMERIC_STD library, you can calculate the vote count manually (though it's more verbose):

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SistemaVotacion IS
PORT (
    j1, j2, j3, j4: IN std_logic;
    l1, l2, l3: OUT std_logic
);
END SistemaVotacion;

ARCHITECTURE SistemaArchitecture OF SistemaVotacion IS
    SIGNAL vote_count : integer RANGE 0 TO 4;
BEGIN
    -- Manual count of '1's using logical operations
    vote_count <= 0 WHEN (j1='0' AND j2='0' AND j3='0' AND j4='0') ELSE
                  1 WHEN (j1='1' XOR j2='1' XOR j3='1' XOR j4='1') AND NOT (j1='1' AND j2='1' OR j1='1' AND j3='1' OR j1='1' AND j4='1' OR j2='1' AND j3='1' OR j2='1' AND j4='1' OR j3='1' AND j4='1') ELSE
                  2 WHEN ( (j1='1' AND j2='1') OR (j1='1' AND j3='1') OR (j1='1' AND j4='1') OR (j2='1' AND j3='1') OR (j2='1' AND j4='1') OR (j3='1' AND j4='1') ) AND NOT (j1='1' AND j2='1' AND j3='1' OR j1='1' AND j2='1' AND j4='1' OR j1='1' AND j3='1' AND j4='1' OR j2='1' AND j3='1' AND j4='1') ELSE
                  3 WHEN (j1='1' AND j2='1' AND j3='1') OR (j1='1' AND j2='1' AND j4='1') OR (j1='1' AND j3='1' AND j4='1') OR (j2='1' AND j3='1' AND j4='1') ELSE
                  4;

    l1 <= '1' WHEN vote_count > 2 ELSE '0';
    l2 <= '1' WHEN vote_count = 2 ELSE '0';
    l3 <= '1' WHEN vote_count = 1 ELSE '0';
END SistemaArchitecture;

This version works with only the STD_LOGIC_1164 library, but the first approach with NUMERIC_STD is far easier to update if you ever change the number of inputs or voting rules.

内容的提问来源于stack exchange，提问作者Adson Henrique