关于SystemVerilog IEEE 1800-2017流拼接赋值a、b为0的疑问

Great question! Let's break this down using the rules defined in SystemVerilog IEEE Std 1800-2017, which your example references.

First, let's recap the basics here:

• a, b, c are all int variables, which are 32 bits each. Together they make up exactly 96 bits, matching the width of the right-hand side value 96'b1.
• The {>>{ ... }} syntax is a rightward streaming assignment—this dictates how the bits from the right-hand side get unpacked into the target variables.

Key Rule for Rightward Streaming Unpacking #

When using {>>{ targets }} = value, the bits from value are assigned starting from:

1. The rightmost target variable in the list, and
2. The least significant bit (LSB) of the input value, working upwards to the most significant bit (MSB).

Let's apply this to your specific line {>>{ a, b, c }} = 96'b1;:

• 96'b1 is a 96-bit value where only the very last bit (bit 0) is 1—all 95 higher bits (bits 1 through 95) are 0.
• We start filling from the rightmost target, c: we take the first 32 bits of the input (bits 0-31). Since only bit 0 is 1, c gets assigned 32'b1 (decimal 1).
• Next, we move to the middle target, b: we take the next 32 bits of the input (bits 32-63). All of these bits are 0, so b gets assigned 32'b0.
• Finally, we fill the leftmost target, a: we take the remaining 32 bits (bits 64-95), which are all 0, so a gets assigned 32'b0.

That's exactly why the comment notes a = 0, b = 0, c = 1—the streaming assignment's right-to-left target order and LSB-first bit allocation leave the leftmost variables with all-zero bit ranges from the input value.

内容的提问来源于stack exchange，提问作者UVMag