Verilog代码always块内赋值reg报错：赋值语句左值语法错误

错误原因分析 #

编译报错的核心问题有两个：

1. case分支标识符未定义：case语句中使用的a、b、c、d未在代码中定义，需替换为之前声明的stateA、stateB、stateC、stateD参数。
2. if/else逻辑块缺失包裹：每个if/else下的多条赋值语句未用begin/end包裹，会导致y_out赋值脱离条件判断独立执行，引发逻辑不符合预期的问题。

修正后的代码 #

module seq(x_in,y_out,Clk,reset);
    input x_in ,Clk, reset;
    output reg y_out;
    reg  [1:0]NextState;
    reg [1:0]CurrentState;

    parameter stateA = 2'b00,
              stateB = 2'b01,
              stateC = 2'b10,
              stateD = 2'b11;

    always @(x_in or CurrentState) begin
        NextState = stateA;
        y_out = 1'b0;

        case(CurrentState)
           stateA : begin
            if(x_in) begin
             NextState = stateC;
             y_out = 1'b0;
            end else begin
             NextState = stateB;
             y_out = 1'b1; 
            end
           end
           stateB : begin
            if(x_in) begin
             NextState = stateD;
             y_out = 1'b1;
            end else begin
             NextState = stateC;
             y_out = 1'b0;
            end
           end
           stateC : begin
            if(x_in) begin
             NextState = stateD;
             y_out = 1'b1;
            end else begin
             NextState = stateB ;
             y_out = 1'b0;
            end
           end
           stateD : begin
            if(x_in) begin
             NextState = stateA;
             y_out = 1'b0;
            end else begin
             NextState = stateC;
             y_out = 1'b1;
            end
           end
           default : begin
             y_out = 1'bx;
             NextState = 2'bxx;
           end
        endcase
    end

    always @(negedge reset ,posedge Clk) begin
     if(!reset)
     CurrentState <= stateA;
     else
     CurrentState <= NextState;
    end
    
endmodule

关键修正说明 #

• 替换case分支的标识符，用已定义的stateA/stateB/stateC/stateD替代未定义的a/b/c/d，解决语法错误。
• 为每个if/else下的多条赋值添加begin/end包裹，确保条件判断同时控制NextState和y_out的赋值，匹配设计逻辑。

内容的提问来源于stack exchange，提问作者Dimitris Papadimitriou