如何向SystemVerilog任务传递变量的引用数组？

尝试向SystemVerilog任务传递变量的引用数组时失败，但单个变量的引用传递可以正常工作。任务目标是接收一组变量，并在每个时钟沿读取它们的实时值。

错误代码示例 #

module tb;
  logic clock = 0;
  logic a = 0;
  logic b = 0;

  task automatic read_vars(ref logic clock, input int clock_edges = 10,
                           const ref logic signal_array[]);
      repeat (clock_edges) begin
        @(posedge clock) $display("@TIME: %t Clock edge", $time);
        for (int i = 0; i < signal_array.size(); i++) begin
          $display("Variable %0d: %0b", i, signal_array[i]);
        end
      end
  endtask

  always begin
    #1 clock = 1;
    #1 clock = 0;
  end

  always begin
    #3 b = 1;
    #3 b = 0;
  end

  always begin
    #7 a = 1;
    #7 a = 0;
  end

  initial begin
    fork
      read_vars(.clock(clock), .signal_array({a, b}));
    join_none

    #1000;
    $finish();
  end
endmodule

报错信息 #

read_vars(.clock(clock), .signal_array({a, b}));
                                             |
xmvlog: *E,BADRFA (tb.sv,25|45): invalid ref argument usage because actual argument is not a variable.  [SystemVerilog].
        module worklib.tb:sv

可正常运行的代码（单个变量引用） #

module tb;
  logic clock = 0;
  logic a = 0;
  logic b = 0;

  task automatic read_vars(ref logic clock, ref logic a, ref logic b, input int clock_edges = 10);
    repeat (clock_edges) begin
      @(posedge clock) begin
        $display("@TIME: %t Clock edge", $time);
        $display("a = %b ", a);
        $display("b = %b ", b);
      end
    end
  endtask

  always begin
    #1 clock = 1;
    #1 clock = 0;
  end

  always begin
    #3 b = 1;
    #3 b = 0;
  end

  always begin
    #7 a = 1;
    #7 a = 0;
  end

  initial begin
    fork
      read_vars(.clock(clock), .a(a), .b(b));
    join_none

    #1000;
    $finish();
  end
endmodule

问题原因与解决方法 #

问题根源 #

你传递给signal_array的{a, b}是位拼接表达式，它会生成一个临时数值，而非可被引用的变量。const ref形参要求实际参数必须是可寻址的变量（如已声明的数组、寄存器等），因为引用需要绑定到固定的内存地址，临时表达式没有固定地址，因此无法作为ref参数传递。

可行解决方案 #

方案1：保留单个ref参数（已验证）

像你第二个代码那样，将每个变量作为独立的ref参数传递，这种方式直接直观，适合变量数量较少的场景。

方案2：数组变量+实时同步

如果必须用数组形式，先声明数组变量，通过always块实时同步数组元素与目标变量的值，再传递数组引用：

module tb;
  logic clock = 0;
  logic a = 0;
  logic b = 0;
  logic signal_array[]; // 声明动态数组

  // 实时同步数组与变量值
  always @(*) begin
    signal_array = '{a, b};
  end

  task automatic read_vars(ref logic clock, input int clock_edges = 10,
                           const ref logic signal_array[]);
      repeat (clock_edges) begin
        @(posedge clock) $display("@TIME: %t Clock edge", $time);
        for (int i = 0; i < signal_array.size(); i++) begin
          $display("Variable %0d: %0b", i, signal_array[i]);
        end
      end
  endtask

  always begin
    #1 clock = 1;
    #1 clock = 0;
  end

  always begin
    #3 b = 1;
    #3 b = 0;
  end

  always begin
    #7 a = 1;
    #7 a = 0;
  end

  initial begin
    signal_array = new[2]; // 初始化数组大小
    fork
      read_vars(.clock(clock), .signal_array(signal_array));
    join_none

    #1000;
    $finish();
  end
endmodule

方案3：用Interface封装变量

如果需要传递的变量较多，可通过interface封装所有信号，再传递interface引用给任务：

interface SignalInterface;
  logic a;
  logic b;
endinterface

module tb;
  logic clock = 0;
  SignalInterface sig_if();

  task automatic read_vars(ref logic clock, input int clock_edges = 10,
                           SignalInterface sig_if);
      repeat (clock_edges) begin
        @(posedge clock) $display("@TIME: %t Clock edge", $time);
        $display("Variable 0: %0b", sig_if.a);
        $display("Variable 1: %0b", sig_if.b);
      end
  endtask

  always begin
    #1 clock = 1;
    #1 clock = 0;
  end

  always begin
    #3 sig_if.b = 1;
    #3 sig_if.b = 0;
  end

  always begin
    #7 sig_if.a = 1;
    #7 sig_if.a = 0;
  end

  initial begin
    fork
      read_vars(.clock(clock), .sig_if(sig_if));
    join_none

    #1000;
    $finish();
  end
endmodule

内容的提问来源于stack exchange，提问作者Prokie