求助：Testbench中寄存器无法更新的问题排查

我设计了一个可根据不同输入实现不同增量的寄存器，在运行Testbench进行验证时，发现寄存器值并未递增，不清楚原因。已尝试切换blocking与nonblocking assignments，但问题仍未解决。现附上相关代码及仿真截图：

设计代码 #

`timescale 1ns / 1ps

module TEMP_P1(
    input clk,
    input reset,

    input inquarter,
    input indime,
    input innickle,
    input inbev1,
    input inbev2,
    input inbev3,
    
    output reg [3:0] outquarter,
    output reg [3:0] outdime,
    output reg [3:0] outnickle,
    output reg [1:0] outbev1,
    output reg [1:0] outbev2,
    output reg [1:0] outbev3
    );
    
    reg [31:0] total;
    reg [3:0] quarter_count;
    reg [3:0] dime_count;
    reg [3:0] nickle_count;
    
    always@(clk)begin
        if(reset)begin
            total = 0;
            quarter_count = 0;
            dime_count = 0;
            nickle_count = 0;
        end else begin
            if (inquarter) begin
                quarter_count = quarter_count + 1;
                total = total + 25;
            end
            if (indime) begin
                dime_count = dime_count + 1;
                total = total + 10;
            end
            if (innickle) begin
                nickle_count = nickle_count + 1;
                total = total + 5;
            end
            
            if ((inbev1 === 1) && ( total >= 100)) begin
                outbev1 = 1;
                total = total - 100;
            end
            if ((inbev2 == 1) && ( total >= 120)) begin
                outbev2 = 1;
                total = total - 120;
            end
            if ((inbev3 == 1) && ( total >= 115)) begin
                outbev3 = 1;
                total = total - 115;
            end
            
            if (total >= 25) begin
                outquarter = 1;
                outdime = 0;
                outnickle = 0;
                total = total - 25;
            end 
            if ((total >= 10) && (total < 25)) begin
                outquarter = 0;
                outdime = 1;
                outnickle = 0;
                total = total - 10;
            end 
            if ((total >= 5) && (total < 10)) begin
                outquarter = 0;
                outdime = 0;
                outnickle = 1;
                total = total - 5;
            end 
        end
        
    end
endmodule

Testbench代码 #

`timescale 1ns / 1ps

module TEMP_P1_TB(
    );
    
    reg clk;
    reg reset;

    reg inquarter;
    reg indime;
    reg innickle;
    reg inbev1;
    reg inbev2;
    reg inbev3;
    
    wire [3:0] outquarter;
    wire [3:0] outdime;
    wire [3:0] outnickle;
    wire [1:0] outbev1;
    wire [1:0] outbev2;
    wire [1:0] outbev3;
    
    TEMP_P1 UUT(.clk(clk), .reset(reset), .inquarter(inquarter), .indime(indime), .innickle(innickle), .inbev1(inbev1), .inbev2(inbev2), .inbev3(inbev3), 
                .outquarter(outquarter), .outdime(outdime), .outnickle(outnickle), .outbev1(outbev1), .outbev2(outbev2), .outbev3(outbev3));
    
    initial begin
        clk = 0;
        reset = 0;
        
        inquarter = 0;
        indime = 0;
        innickle = 0;
        inbev1 = 0;
        inbev2 = 0;
        inbev3 = 0;
        #10;
        
        reset = 1;
        #1
        reset = 0;
        #1
        
        inquarter = 1;
        #1;
        
        inquarter = 0;
        #1;
        
        inquarter = 1;
        #1;
        
        inquarter = 0;
        #1;
        
        inquarter = 1;
        #1;
        
        inquarter = 0;
        #1;
        
        inquarter = 1;
        #1;
        
        inquarter = 0;
        #1;
        
        inquarter = 1;
        #1;
        
        inquarter = 0;
        #1;
        
        inbev1 = 1;
        #1;
        
        inbev1 = 0;
        #1;
        
    end
    
    always begin
        #1 clk = ~clk;
    end
    
endmodule

仿真截图 #

内容的提问来源于stack exchange，提问作者Billy Black