Verilog多模块输出多驱动冲突问题及解决方法咨询

三个内部赋值顺序不同的Verilog模块 #

Block1 #

module block1 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
    outA = inA;
    outB = outA;
    outC = outB;
end
endmodule

Block2 #

module block2 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
    outC = outB;
    outA = inA;
    outB = outA;
end
endmodule

Block3 #

module block3 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
    outB = outA;
    outA = inA;
    outC = outB;
end
endmodule

顶层模块ordering1的例化代码 #

module ordering1 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
//reg outA, outB, outC;

block1 block1_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
block2 block2_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
block3 block3_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
endmodule

编译错误信息 #

Error (12014): Net "outA", which fans out to "outA", cannot be assigned more than one value
Error (12015): Net is fed by "block1:block1_inst|outA"
Error (12015): Net is fed by "block2:block2_inst|outA"
Error (12015): Net is fed by "block3:block3_inst|outA"

Error (12014): Net "outB", which fans out to "outB", cannot be assigned more than one value
Error (12015): Net is fed by "block1:block1_inst|outB"
Error (12015): Net is fed by "block2:block2_inst|outB"
Error (12015): Net is fed by "block3:block3_inst|outB"

Error (12014): Net "outC", which fans out to "outC", cannot be assigned more than one value
Error (12015): Net is fed by "block1:block1_inst|outC"
Error (12015): Net is fed by "block2:block2_inst|outC"
Error (12015): Net is fed by "block3:block3_inst|outC"

问题原因与解决方法 #

核心原因 #

你把三个模块的outA/outB/outC全部绑定到顶层的同一个输出信号上，导致同一个网线被三个寄存器同时驱动，Verilog不允许这种非线网类型的多驱动冲突（寄存器输出属于强驱动，多个强驱动会导致逻辑歧义）。

解决方法 #

给每个模块的输出分配独立的顶层信号，修改后的顶层模块代码如下：

module ordering1 (clk, inA, 
                  outA_1, outB_1, outC_1,
                  outA_2, outB_2, outC_2,
                  outA_3, outB_3, outC_3);
input clk, inA;

// 为三个模块分别定义独立的输出端口
output outA_1, outB_1, outC_1;
output outA_2, outB_2, outC_2;
output outA_3, outB_3, outC_3;

// 例化时将每个模块的输出连接到对应独立信号
block1 block1_inst (
    .clk(clk), 
    .inA(inA), 
    .outA(outA_1), 
    .outB(outB_1), 
    .outC(outC_1)
);

block2 block2_inst (
    .clk(clk), 
    .inA(inA), 
    .outA(outA_2), 
    .outB(outB_2), 
    .outC(outC_2)
);

block3 block3_inst (
    .clk(clk), 
    .inA(inA), 
    .outA(outA_3), 
    .outB(outB_3), 
    .outC(outC_3)
);
endmodule

补充说明 #

如果你的需求是对比三个模块因赋值顺序不同产生的输出差异，这种独立端口的方式能最直观地呈现结果，每个模块的输出互不干扰，避免了驱动冲突问题。

内容的提问来源于stack exchange，提问作者CJ. T