VHDL代码语法错误求助：第166行process语句附近报错

核心语法错误 #

你遇到的Error: Syntax error near 'process'是因为第166行的process被写在了Practice实体的Behavioral架构之外。VHDL要求所有并发语句（包括process）必须放在architecture的begin和end Behavioral;之间，而你把这段7段码更新的process写在了架构闭合语句之后，编译器无法识别该位置的语法结构。

修正后的完整代码 #

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ss_driver is
    port (
        -- Inputs
        segment_a : in std_logic;
        segment_b : in std_logic;
        segment_c : in std_logic;
        segment_d : in std_logic;
        segment_e : in std_logic;
        segment_f : in std_logic;
        segment_g : in std_logic;
        ss_dp : in std_logic; -- optional decimal point input
        -- Outputs
        ss_segments : out std_logic_vector(6 downto 0)
    );
end ss_driver;

architecture Behavioral of ss_driver is
begin
    -- Define the 7-segment display driver logic here
    ss_segments <= not (segment_a & segment_b & segment_c & segment_d & segment_e & segment_f & segment_g);

    -- Connect the decimal point segment to the ss_dp input
    ss_segments(6) <= not ss_dp;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Practice is
    Port ( clk : in STD_LOGIC;
           unhappy_btn : in STD_LOGIC;
           neutral_btn : in STD_LOGIC;
           pleased_btn : in STD_LOGIC;
           delighted_btn : in STD_LOGIC;
           -- Pause & Reset Functionality 
           pause_reset_btn : in STD_LOGIC;
           -- Defining warning light output signal
           warning_light : out STD_LOGIC;
           -- Defining 7-segment displays
           ss_segments : out STD_LOGIC_VECTOR (6 downto 0);
           display_0 : out STD_LOGIC_VECTOR(6 downto 0);
           display_1 : out STD_LOGIC_VECTOR(6 downto 0);
           display_2 : out STD_LOGIC_VECTOR(6 downto 0);
           display_3 : out STD_LOGIC_VECTOR(6 downto 0));
          
end Practice;

architecture Behavioral of Practice is
    -- Declare the state type and signals
    type satisfaction_state is (idle, unhappy, neutral, pleased, delighted, pause, paused, reset);
    signal current_state, next_state : satisfaction_state;
    
    -- Declare the count signals
    signal unhappy_count, neutral_count, pleased_count, delighted_count : integer range 0 to 9999 := 0;
    signal pause_count, reset_count : integer range 0 to 9999 := 0;
    
    -- Declare reset_pending signal
    signal reset_pending : boolean := false;
    
    -- Declare display signals
    signal display_unhappy, display_neutral, display_pleased, display_delighted : STD_LOGIC_VECTOR(6 downto 0);
    signal display_count : integer range 0 to 99999 :=0;
    signal display_value : STD_LOGIC_VECTOR(6 downto 0); -- 修正为7位，匹配7段码输出
    signal segment_a, segment_b, segment_c, segment_d, segment_e, segment_f, segment_g : std_logic;
    signal display_counter : integer range 0 to 3;
    
begin
-- 状态同步process：将next_state同步到current_state，原代码遗漏此步骤导致状态无法流转
process(clk)
begin
    if rising_edge(clk) then
        current_state <= next_state;
        -- 检测reset_pending，触发重置状态
        if reset_pending then
            current_state <= reset;
        end if;
    end if;
end process;

-- 状态转移与计数逻辑process
process(clk, current_state, reset_pending)
begin
    if rising_edge(clk) then
    -- Set the default next state
    next_state <= current_state;
    
    case current_state is
        -- Idle state
        when idle =>
            -- Check which button was pressed
            if unhappy_btn = '1' then
                next_state <= unhappy;
            elsif neutral_btn = '1' then
                next_state <= neutral;
            elsif pleased_btn = '1' then
                next_state <= pleased;
            elsif delighted_btn = '1' then
                next_state <= delighted;
            elsif pause_reset_btn = '1' then
                next_state <= pause;
            end if;
            
        -- Unhappy state
        when unhappy =>
            if unhappy_btn = '1' then
                unhappy_count <= unhappy_count + 1;
            end if;
            display_unhappy <= std_logic_vector(to_unsigned(unhappy_count, 7));
            next_state <= idle;
            
        -- Neutral state
        when neutral =>
            if neutral_btn = '1' then
                neutral_count <= neutral_count + 1;
            end if;
            display_neutral <= std_logic_vector(to_unsigned(neutral_count, 7));
            next_state <= idle;
            
        -- Pleased state
        when pleased =>
            if pleased_btn = '1' then
                pleased_count <= pleased_count + 1;
            end if;
            display_pleased <= std_logic_vector(to_unsigned(pleased_count, 7));
            next_state <= idle;

            
        -- Delighted state
        when delighted =>
            if delighted_btn = '1' then
                delighted_count <= delighted_count + 1;
            end if;
            display_delighted <= std_logic_vector(to_unsigned(delighted_count, 7));
            next_state <= idle;
            
        -- Pause state
        when pause =>
            reset_pending <= false;
            pause_count <= 1;
            next_state <= paused;
            
        -- Paused state
        when paused =>
            -- Count up for 10 clock cycles
            if pause_count < 10 then
                pause_count <= pause_count + 1;
                next_state <= paused;
            -- If reset button is pressed, set reset_pending signal
            elsif pause_reset_btn = '1' then
                reset_pending <= true;
            -- If any satisfaction button is pressed, return to pause state
            elsif unhappy_btn = '1' or neutral_btn = '1' or pleased_btn = '1' or delighted_btn = '1' then
                next_state <= pause;
            end if;
            
        -- Reset state
        when reset =>
            unhappy_count <= 0;
            neutral_count <= 0;
            pleased_count <= 0;
            delighted_count <= 0;
            display_count <= 0;
            reset_count <= 0;
            reset_pending <= false;
            next_state <= idle;
            
    end case;
end if;
end process;

-- 7段码更新process：移到架构内部
process(clk)
begin
    if rising_edge(clk) then
        case current_state is
            when unhappy =>
                display_count <= unhappy_count;
            when neutral =>
                display_count <= neutral_count;
            when pleased =>
                display_count <= pleased_count;
            when delighted =>
                display_count <= delighted_count;
            when others =>
                display_count <= 0;
        end case;
        
        
        -- Convert the count to a 7-segment display value
        case display_count is
            when 0 =>
                display_value <= "0000001"; -- 0（共阴极码，共阳极需取反）
            when 1 =>
                display_value <= "1001111"; -- 1
            when 2 =>
                display_value <= "0010010"; -- 2
            when 3 =>
                display_value <= "0000110"; -- 3
            when 4 =>
                display_value <= "1001100"; -- 4
            when 5 =>
                display_value <= "0100100"; -- 5
            when 6 =>
                display_value <= "0100000"; -- 6
            when 7 =>
                display_value <= "0001111"; -- 7
            when 8 =>
                display_value <= "0000000"; -- 8
            when 9 =>
                display_value <= "0000100"; -- 9
            when others =>
                display_value <= "1111111"; -- Error
        end case;
    end if;
end process;

-- 映射7段码到输出端口
display_0 <= display_value;
-- 多数码管需添加多路复用逻辑驱动display_1~display_3
end Behavioral;

额外修正说明 #

1. 状态同步逻辑：原代码仅更新next_state但未同步到current_state，导致状态无法正常流转，新增专用process处理状态同步。
2. display_value位数修正：原代码定义为8位，7段码仅需7位，修正后匹配输出端口宽度。
3. reset触发逻辑：补充reset_pending检测，确保能正确进入重置状态。
4. 输出映射：添加display_0 <= display_value;将转换后的段码连接到实际输出，多数码管场景需扩展多路复用逻辑。

其他注意事项 #

• 硬件中按钮需添加消抖逻辑，避免机械抖动导致计数错误。
• ss_driver实体未被Practice实例化，若需使用该驱动，需在架构中添加组件实例化代码。
• 段码需根据硬件类型（共阴极/共阳极）调整是否取反。

内容的提问来源于stack exchange，提问作者Taksiepacze