Verilog 16x8 BRAM排序模块数据读取与回写问题技术求助

Hey there! Let's break down the issues you're facing with your Verilog sorting module and fix them step by step.

Core Problems in Your Current Code #

1. No Data Link Between sort and memory: The internal RAM in your sort module is completely separate from the external memory module—they don't share any data, which is why only the internal RAM gets sorted while the actual memory remains unchanged.
2. Missing Read/Write Control: Your sort module wasn't actively reading data from memory into its internal buffer, nor was it writing the sorted data back to memory afterward. You were just passing external control signals directly to memory without orchestrating the data flow.

Fixed Implementation #

We'll use a state machine to manage the full workflow: idle → read all data from memory → sort → write sorted data back to memory → done.

Modified sort Module

`timescale 1ns / 1ps
module sort(clk, sort, done, mem_clk, mem_we, mem_en, mem_addr, mem_di, mem_do);
    input clk;
    input sort;
    output reg done;
    
    // Interface to control the external memory module
    output reg mem_clk;
    output reg mem_we;
    output reg mem_en;
    output reg [3:0] mem_addr;
    output reg signed [4:0] mem_di;
    input signed [4:0] mem_do;
    
    reg signed [7:0] internal_ram [15:0]; // Internal buffer for sorting
    integer i, j;
    reg [3:0] count; // Address counter for read/write operations
    reg [2:0] state; // State machine state
    
    // State definitions
    localparam IDLE = 3'b000;
    localparam READ_MEM = 3'b001;
    localparam SORTING = 3'b010;
    localparam WRITE_MEM = 3'b011;
    localparam DONE = 3'b100;
    
    always @(posedge clk) begin
        mem_clk <= clk; // Sync memory clock to system clock
        
        case(state)
            IDLE: begin
                done <= 1'b0;
                mem_we <= 1'b0;
                mem_en <= 1'b0;
                mem_addr <= 4'b0000;
                count <= 4'b0000;
                
                if(sort) begin
                    state <= READ_MEM;
                    mem_en <= 1'b1; // Enable memory for reading
                end
            end
            
            READ_MEM: begin
                // Read current memory address into internal buffer
                internal_ram[count] <= mem_do;
                count <= count + 1'b1;
                mem_addr <= count + 1'b1; // Prepare next address
                
                if(count == 4'b1111) begin // Finished reading all 16 entries
                    state <= SORTING;
                    mem_en <= 1'b0;
                    count <= 4'b0000;
                end
            end
            
            SORTING: begin
                // Bubble sort (executes in one clock cycle for simulation; optimize for multi-cycle in hardware)
                for(i=0; i<15; i=i+1) begin
                    for(j=0; j<15-i; j=j+1) begin
                        if(internal_ram[j] > internal_ram[j+1]) begin
                            internal_ram[j] <= internal_ram[j+1];
                            internal_ram[j+1] <= internal_ram[j];
                        end
                    end
                end
                state <= WRITE_MEM;
                mem_en <= 1'b1; // Enable memory for writing
                mem_we <= 1'b1;
                mem_addr <= 4'b0000;
            end
            
            WRITE_MEM: begin
                // Write sorted internal data back to memory
                mem_di <= internal_ram[count];
                mem_addr <= count;
                count <= count + 1'b1;
                
                if(count == 4'b1111) begin // Finished writing all 16 entries
                    state <= DONE;
                    mem_we <= 1'b0;
                    mem_en <= 1'b0;
                end
            end
            
            DONE: begin
                done <= 1'b1;
                if(!sort) begin // Return to idle when sort signal is low
                    state <= IDLE;
                end
            end
            
            default: state <= IDLE;
        endcase
    end
endmodule

Modified Testbench

Now the testbench only handles memory initialization and triggers the sort signal—all memory control during sorting is managed by the sort module:

`timescale 1ns / 1ps
module sort_tb();
    reg clk;
    reg sort;
    wire done;
    
    // Memory interface signals
    reg mem_we_init;
    reg mem_en_init;
    reg [3:0] mem_addr_init;
    reg signed [4:0] mem_di_init;
    wire signed [4:0] mem_do;
    
    // Instantiate memory module
    memory mem(
        .clk(clk),
        .we(mem_we_init),
        .en(mem_en_init),
        .addr(mem_addr_init),
        .di(mem_di_init),
        .do(mem_do)
    );
    
    // Instantiate sort module (controls memory during sorting)
    sort srt(
        .clk(clk),
        .sort(sort),
        .done(done),
        .mem_clk(clk),
        .mem_we(mem_we_init),
        .mem_en(mem_en_init),
        .mem_addr(mem_addr_init),
        .mem_di(mem_di_init),
        .mem_do(mem_do)
    );
    
    initial begin
        sort = 1'b0;
        clk = 1'b0;
        mem_en_init = 1'b1;
        mem_we_init = 1'b1;
        
        // Initialize memory with test data
        mem_addr_init = 4'h0; mem_di_init = -8; #10;
        mem_addr_init = 4'h1; mem_di_init = -5; #10;
        mem_addr_init = 4'h2; mem_di_init = -6; #10;
        mem_addr_init = 4'h3; mem_di_init = -3; #10;
        mem_addr_init = 4'h4; mem_di_init = -4; #10;
        mem_addr_init = 4'h5; mem_di_init = -1; #10;
        mem_addr_init = 4'h6; mem_di_init = -2; #10;
        mem_addr_init = 4'h7; mem_di_init = 1; #10;
        mem_addr_init = 4'h8; mem_di_init = 0; #10;
        mem_addr_init = 4'h9; mem_di_init = 3; #10;
        mem_addr_init = 4'hA; mem_di_init = 2; #10;
        mem_addr_init = 4'hB; mem_di_init = 5; #10;
        mem_addr_init = 4'hC; mem_di_init = 4; #10;
        mem_addr_init = 4'hD; mem_di_init = 7; #10;
        mem_addr_init = 4'hE; mem_di_init = 6; #10;
        mem_addr_init = 4'hF; mem_di_init = 8; #10;
        
        // Trigger sorting process
        mem_we_init = 1'b0;
        sort = 1'b1;
        #200; // Wait for sorting and write-back to complete
        
        // Verify sorted memory data here if needed
        sort = 1'b0;
        #50;
        $finish;
    end
    
    always #5 clk = ~clk;
endmodule

Key Improvements Explained #

• State Machine Orchestration: The state machine ensures a clear, sequential flow of operations, preventing control conflicts and ensuring data is read/sorted/written correctly.
• Direct Data Flow: The sort module now actively reads all memory entries into its internal buffer before sorting, then writes the sorted data back to memory.
• Controlled Memory Interface: All memory control signals (we, en, addr) are managed by the sort module during the sorting process, eliminating external interference.

内容的提问来源于stack exchange，提问作者Kerim Turak