VHDL报错：无法在当前时钟沿实现寄存器赋值问题求助

问题代码 #

--! start state logic
start_int <= start;
ssl_edge_detect_proc: process(start_int,clk)
begin
   if rising_edge(start_int) then
     start_edge_old<='1';
  else
     start_edge_old<='0';
  end if;
 start_edge<=start_edge_old;
 end process;

SslProc: process(send_state,start_int,clk,rst)
variable start_variable : std_logic:='0';
BEGIN   
  if rising_edge(clk) then 
    if rst = '1' then
       start_i <= '0';
       ssl_current_state <= ssl_idle;
    else
    start_i <= '0';
    CASE ssl_current_state IS
        WHEN ssl_idle =>if start_edge= '1' and send_state=idle then 
                           ssl_current_state <= ssl_start;-- 此行报错
                                        start_variable:='1';
                                    else
                        ssl_current_state <= ssl_idle;-- 此行也报错
                                    end if;
        WHEN ssl_start =>
                start_i <= '1';
            IF send_state=send_modecmd THEN
                               ssl_current_state <= ssl_run;
            END IF;
        WHEN ssl_run =>
            IF send_state=idle or reset_proc ='1' THEN
                               ssl_current_state <= ssl_idle;
            END IF;
    END CASE;
    end if;
     end if;
END PROCESS sslProc;

问题描述 #

在第二个进程的ssl_idle状态中，对ssl_current_state进行赋值时，Quartus抛出报错：couldn't implement registers for assignments on this clock edge。ModelSim仿真结果正常，但综合工具报错；注释掉ssl_idle状态中的这两个赋值语句后报错消失。

问题原因 #

1. 异步边沿检测逻辑违规：第一个进程以start_int作为敏感信号，生成的start_edge是异步信号，未同步到系统时钟clk。同步状态机使用异步信号作为跳转条件时，综合器无法正确推断同步寄存器，导致报错。
2. 状态机敏感列表错误：状态机进程SslProc的敏感列表包含了send_state、start_int等非时钟/复位信号，不符合同步状态机的设计规范，干扰了综合器的寄存器推断。
3. 冗余赋值加剧冲突：ssl_idle状态else分支的ssl_current_state <= ssl_idle属于冗余赋值（状态机未显式赋值时会自动保持当前状态），但异步信号的存在让综合器误判逻辑需求，进一步触发报错。

解决方案 #

1. 修正边沿检测逻辑（同步化处理）

将外部异步start信号同步到系统时钟域，再检测上升沿，生成仅持续一个时钟周期的同步脉冲：

--! 同步并检测start信号上升沿
signal start_sync1, start_sync2 : std_logic;
begin
-- 两级寄存器同步外部异步信号，避免亚稳态
process(clk, rst)
begin
    if rst = '1' then
        start_sync1 <= '0';
        start_sync2 <= '0';
    elsif rising_edge(clk) then
        start_sync1 <= start;
        start_sync2 <= start_sync1;
    end if;
end process;

-- 生成同步后的上升沿脉冲
start_edge <= start_sync1 and not start_sync2;

2. 修正状态机进程

• 敏感列表仅保留clk和rst（同步状态机标准配置）；
• 移除ssl_idle状态中冗余的赋值语句：

SslProc: process(clk, rst)
    variable start_variable : std_logic := '0';
begin   
    if rising_edge(clk) then 
        if rst = '1' then
            start_i <= '0';
            ssl_current_state <= ssl_idle;
        else
            start_i <= '0';
            CASE ssl_current_state IS
                WHEN ssl_idle => 
                    if start_edge = '1' and send_state = idle then 
                        ssl_current_state <= ssl_start;
                        start_variable := '1';
                    end if;
                WHEN ssl_start =>
                    start_i <= '1';
                    IF send_state = send_modecmd THEN
                        ssl_current_state <= ssl_run;
                    END IF;
                WHEN ssl_run =>
                    IF send_state = idle or reset_proc = '1' THEN
                        ssl_current_state <= ssl_idle;
                    END IF;
            END CASE;
        end if;
    end if;
END PROCESS sslProc;

说明 #

修改后的代码确保所有状态机输入信号都同步到系统时钟，符合同步电路设计规范，Quartus可以正确推断寄存器，同时保留原有功能，仿真和综合均可正常通过。

内容的提问来源于stack exchange，提问作者Srikanth