VHDL仿真报错(vsim-3807)：out1端口组件与实体类型不匹配求助

我查遍了同类问题的提问，要么信息不足没得到解答，要么方案不适用我的场景。在进行多路分配器仿真时出现如下错误：

# vsim -novopt -c -t 1ps -L fiftyfivenm -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.demultiplexer_vhd_vec_tst 

# Start time: 19:44:15 on Apr 10,2023

# Loading std.standard

# Loading std.textio(body)

# Loading ieee.std_logic_1164(body)

# Loading work.demultiplexer_vhd_vec_tst(demultiplexer_arch)

# Loading ieee.vital_timing(body)

# Loading ieee.vital_primitives(body)

# Loading fiftyfivenm.fiftyfivenm_atom_pack(body)

# Loading fiftyfivenm.fiftyfivenm_components

# Loading work.demultiplexer(structure)

# ** Fatal: (vsim-3807) Types do not match between component and entity for port "out1".

# Time: 0 ps  Iteration: 0  Instance: /demultiplexer_vhd_vec_tst/i1 File: LabNine.vho Line: 39

# FATAL ERROR while loading design

# Error loading design

# End time: 19:44:15 on Apr 10,2023, Elapsed time: 0:00:00

# Errors: 1 Warnings: 0

Error

核心VHDL代码 #

ENTITY demultiplexer IS
    PORT (  out1 : OUT BIT_VECTOR (0 TO 7); 
            out2 : OUT BIT_VECTOR (0 TO 7); 
            out3 : OUT BIT_VECTOR (0 TO 7); 
            CLR : OUT BIT; 
            inbus : IN BIT_VECTOR(0 TO 7); 
            S0 : IN BIT; S1 : IN BIT);
END demultiplexer;

ARCHITECTURE dataflow OF demultiplexer IS
BEGIN
process(S0, S1)
    BEGIN
        IF (S0 = '0') and (S1 = '0') THEN
            CLR <= '1';
        ELSIF (S0 = '1') and (S1 = '0') THEN
            out1(0) <= inbus(0);
            out1(1) <= inbus(1);
            out1(2) <= inbus(2);
            out1(3) <= inbus(3);
            out1(4) <= inbus(4);
            out1(5) <= inbus(5);
            out1(6) <= inbus(6);
            out1(7) <= inbus(7);
            CLR <= '0';
        ELSIF (S0 = '0') and (S1 = '1') THEN
            out2(0) <= inbus(0);
            out2(1) <= inbus(1);
            out2(2) <= inbus(2);
            out2(3) <= inbus(3);
            out2(4) <= inbus(4);
            out2(5) <= inbus(5);
            out2(6) <= inbus(6);
            out2(7) <= inbus(7);
            CLR <= '0';
        ELSIF (S0 = '1') and (S1 = '1') THEN
            out3(0) <= inbus(0);
            out3(1) <= inbus(1);
            out3(2) <= inbus(2);
            out3(3) <= inbus(3);
            out3(4) <= inbus(4);
            out3(5) <= inbus(5);
            out3(6) <= inbus(6);
            out3(7) <= inbus(7);
            CLR <= '0';
        END IF;
    END process;
END dataflow;

仿真波形设置 #

• S0：50ns跳变周期
• S1：100ns跳变周期
• inbus[0]：200ns跳变周期
• inbus[1]：400ns跳变周期
• inbus[2]：800ns跳变周期
• inbus[3]：1600ns跳变周期
• inbus[4]：3200ns跳变周期
• inbus[5]：6400ns跳变周期
• inbus[6]：12800ns跳变周期
• inbus[7]：25600ns跳变周期
• 仿真结束时间：51200ns

LabNine.vho相关片段（报错行附近） #

ARCHITECTURE structure OF demultiplexer IS

SIGNAL gnd : std_logic := '0';

SIGNAL vcc : std_logic := '1';

SIGNAL unknown : std_logic := 'X';

SIGNAL devoe : std_logic := '1';

SIGNAL devclrn : std_logic := '1';

SIGNAL devpor : std_logic := '1';

SIGNAL ww_devoe : std_logic;

SIGNAL ww_devclrn : std_logic;

SIGNAL ww_devpor : std_logic;

SIGNAL ww_out1 : std_logic_vector(0 TO 7);

SIGNAL ww_out2 : std_logic_vector(0 TO 7);

SIGNAL ww_out3 : std_logic_vector(0 TO 7);

SIGNAL ww_CLR : std_logic;

SIGNAL ww_inbus : std_logic_vector(0 TO 7);

SIGNAL ww_S0 : std_logic;

SIGNAL ww_S1 : std_logic;

SIGNAL \out1[7]~output_o\ : std_logic;

SIGNAL \out1[6]~output_o\ : std_logic;

SIGNAL \out1[5]~output_o\ : std_logic;

SIGNAL \out1[4]~output_o\ : std_logic;

SIGNAL \out1[3]~output_o\ : std_logic;

SIGNAL \out1[2]~output_o\ : std_logic;

SIGNAL \out1[1]~output_o\ : std_logic;

SIGNAL \out1[0]~output_o\ : std_logic;

SIGNAL \out2[7]~output_o\ : std_logic;

SIGNAL \out2[6]~output_o\ : std_logic;

SIGNAL \out2[5]~output_o\ : std_logic;

SIGNAL \out2[4]~output_o\ : std_logic;

SIGNAL \out2[3]~output_o\ : std_logic;

SIGNAL \out2[2]~output_o\ : std_logic;

SIGNAL \out2[1]~output_o\ : std_logic;

SIGNAL \out2[0]~output_o\ : std_logic;

SIGNAL \out3[7]~output_o\ : std_logic;

SIGNAL \out3[6]~output_o\ : std_logic;

SIGNAL \out3[5]~output_o\ : std_logic;

SIGNAL \out3[4]~output_o\ : std_logic;

SIGNAL \out3[3]~output_o\ : std_logic;

SIGNAL \out3[2]~output_o\ : std_logic;

SIGNAL \out3[1]~output_o\ : std_logic;

SIGNAL \out3[0]~output_o\ : std_logic;

...

该多路分配器在DE10-Lite板卡上实物演示完全正常，但仿真时出现上述错误，恳请提供帮助。

内容的提问来源于stack exchange，提问作者Frasher Gray