Xilinx KC705 FPGA的XADC GPIO使用问题：示波器无输出排查

环境 #

• AMD Kintex-7 KC705评估套件
• Vivado 2022.2开发环境

问题现象 #

尝试将自制时钟信号通过XADC的GPIO_0引脚输出，示波器无法检测到信号。已通过LED验证时钟生成逻辑正常，但项目编译过程中出现LVCMOS相关错误。

已做配置 #

XADC GPIO引脚配置片段（参考Xilinx官方引脚信息） #

set_property PACKAGE_PIN AA27 [get_ports XADC_GPIO_3] 
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3] 
set_property PACKAGE_PIN AB28 [get_ports XADC_GPIO_2] 
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2] 
set_property PACKAGE_PIN AA25 [get_ports XADC_GPIO_1] 
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1] 
set_property PACKAGE_PIN AB25 [get_ports XADC_GPIO_0] 
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0] 

测试Verilog代码 #

`timescale 1ns / 1ps

module top(
    input rst,
    input clk_p,
    input clk_n,
    //output [7:0] leds,
    output gpio_0
);

wire            clk;

IBUFDS #(
    .DIFF_TERM("FALSE"),
    .IBUF_LOW_PWR("TRUE"),      
    .IOSTANDARD("DEFAULT")      
) IBUFDS_inst (
    .O(clk),                    
    .I(clk_p),               
    .IB(clk_n)                  
);

reg     [31:0]  counter;
always @ (posedge clk or posedge rst)
    if(rst)
        counter <= 0;
    else
        counter <= counter + 1'b1;

//assign            leds = counter[31:24];
assign          gpio_0 = counter[10];
endmodule

完整XDC约束文件 #

set_property PACKAGE_PIN AD12 [get_ports clk_p]
set_property IOSTANDARD LVDS [get_ports clk_p]
set_property IOSTANDARD LVCMOS15 [get_ports rst]
set_property PACKAGE_PIN G12 [get_ports rst]
#set_property PACKAGE_PIN AB8 [get_ports {leds[0]}]
#set_property PACKAGE_PIN AA8 [get_ports {leds[1]}]
#set_property PACKAGE_PIN AC9 [get_ports {leds[2]}]
#set_property PACKAGE_PIN AB9 [get_ports {leds[3]}]
#set_property PACKAGE_PIN AE26 [get_ports {leds[4]}]
#set_property PACKAGE_PIN G19 [get_ports {leds[5]}]
#set_property PACKAGE_PIN E18 [get_ports {leds[6]}]
#set_property PACKAGE_PIN F16 [get_ports {leds[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {leds[0]}]
set_property PACKAGE_PIN AB25 [get_ports gpio_0]
set_property IOSTANDARD LVCMOS33 [get_ports gpio_0]

咨询问题 #

1. XADC GPIO的正确使用方法是什么？
2. KC705评估板上的XADC GPIO_0端口是否可用？

内容的提问来源于stack exchange，提问作者Jihun Kim