基于VHDL的MIPS处理器寄存器文件写入操作报错排查

错误原因分析 #

报错“Line 35: Formal has no actual or default value.”核心原因有两点：

• Flopr组件定义了GENERIC(n:integer)参数，但实例化时未指定该参数的具体值，编译器无法确定寄存器位宽；
• 写操作译码器错误使用了读地址read_sel1作为输入，逻辑不符合MIPS寄存器文件的写规则。

具体修复步骤 #

1. 为Flopr实例化指定GENERIC参数 #

Flopr是带位宽参数的通用寄存器组件，实例化时必须明确指定n=32（对应32位寄存器），同时推荐使用命名端口映射替代位置映射，避免端口顺序错误：

原代码：

reg: Flopr port map (clk, reset_flopr, write_ena AND decoder_output(i), write_data, reg_outputs(i));

修改为：

reg: Flopr 
    GENERIC MAP(n => 32)
    PORT MAP(
        CLK => clk,
        RST => reset_flopr,
        Load => write_ena AND decoder_output(i),
        D => write_data,
        Q => reg_outputs(i)
    );

2. 修正译码器的输入地址 #

写操作需要通过write_sel选择目标寄存器，而非读地址read_sel1，同样改用命名映射提升代码可读性：

原代码：

decoder1: Decoder_5x32 port map (read_sel1,decoder_output);

修改为：

decoder1: Decoder_5x32
    PORT MAP(
        Selector => write_sel,
        Data_Out => decoder_output
    );

3. 补充读操作逻辑（可选但必要） #

当前代码仅实现写操作，需补充读操作的寄存器选择逻辑，可直接用进程实现数组索引替代MUX：

-------------------------------------------------------------------------------------------
----------------------------------Read Implementation--------------------------------------
-------------------------------------------------------------------------------------------
read_data1: process(read_sel1, reg_outputs)
begin
    data1 <= reg_outputs(to_integer(unsigned(read_sel1)));
end process;

read_data2: process(read_sel2, reg_outputs)
begin
    data2 <= reg_outputs(to_integer(unsigned(read_sel2)));
end process;

完整修复后的Reg架构代码 #

architecture Behavioral of Reg is

--Signal Declaration
signal decoder_output: STD_LOGIC_VECTOR (31 downto 0);
signal reset_flopr: STD_LOGIC := '0';
type reg_type is array (0 to 31 ) of std_logic_vector (31 downto 0);
signal reg_outputs: reg_type;

begin

-------------------------------------------------------------------------------------------
----------------------------------Write Implementation-------------------------------------
-------------------------------------------------------------------------------------------

--Write Decoder
decoder1: Decoder_5x32
    PORT MAP(
        Selector => write_sel,
        Data_Out => decoder_output
    );

--Registers
reg_gen : for i in 0 to 31 generate
  reg: Flopr 
      GENERIC MAP(n => 32)
      PORT MAP(
          CLK => clk,
          RST => reset_flopr,
          Load => write_ena AND decoder_output(i),
          D => write_data,
          Q => reg_outputs(i)
      );
end generate reg_gen;

-------------------------------------------------------------------------------------------
----------------------------------Read Implementation--------------------------------------
-------------------------------------------------------------------------------------------
read_data1: process(read_sel1, reg_outputs)
begin
    data1 <= reg_outputs(to_integer(unsigned(read_sel1)));
end process;

read_data2: process(read_sel2, reg_outputs)
begin
    data2 <= reg_outputs(to_integer(unsigned(read_sel2)));
end process;

end Behavioral;

内容的提问来源于stack exchange，提问作者Ahmed El-Baramony