Verilog FIFO仿真报错：无法分配未解析wire问题求助

核心问题分析 #

错误根源在测试平台代码的端口声明和赋值逻辑：

• 你把DUT的输出信号DATAOUT、full、empty错误声明为reg类型，Verilog中模块的输出在测试平台里必须用wire类型，由DUT内部驱动，不能手动赋值。
• 测试平台里手动对full、empty、DATAOUT赋值，和DUT的驱动产生冲突，导致仿真器认为这些信号是“未解析连线”。
• 测试平台中声明的state是无效的，因为它和DUT内部的state无关，$monitor里引用的state无法获取DUT内部状态。

修正后的测试平台代码 #

`timescale 1ns/1ps
module jFIFOTb;
  // 修正：DUT的输出必须用wire类型
  wire [7:0] DATAOUT;
  wire full, empty;
  reg clock, reset, wn, rn;
  reg [7:0] DATAIN;

  jFIFO DUT(DATAOUT, full, empty, clock, reset, wn, rn, DATAIN);

  initial begin 
    clock = 0;
    forever #1 clock = ~clock;
  end 

  // 修正：用层次化引用获取DUT内部的state信号
  initial begin 
    $monitor ("[$t]	state = %b	DATAIN = %d	DATAOUT = %d	wn = %b	rn =%b	reset = %b	full=%b	empty=%b",
              $time, DUT.state, DATAIN, DATAOUT, wn, rn, reset, full, empty);
  end

  initial begin
    DATAIN = 8'd0;
    reset = 1; // 先复位，符合FIFO初始化逻辑
    wn = 0; rn = 0;
    #2 reset = 0; // 复位持续2个时钟周期
  end

  initial begin 
    // 写入数据
    #5 wn = 1; rn = 0;
    #2 DATAIN = 8'd100;
    #2 DATAIN = 8'd150;
    #2 DATAIN = 8'd200;
    #2 DATAIN = 8'd40;
    #2 DATAIN = 8'd70;
    #2 DATAIN = 8'd65;
    #2 DATAIN = 8'd15;
    #2 DATAIN = 8'd55;
    // 读取数据
    #2 wn = 0; rn = 1;
    repeat(8) #2 rn = 1;
    #2 $stop;
  end
 
endmodule

FIFO模块的额外优化（解决满/空判断逻辑缺陷） #

你当前的FIFO满判断逻辑只覆盖了wptr=7且rptr=0的情况，无法处理“写-读-再写”后的满状态。添加计数器跟踪存储数据量，可更准确判断满/空：

module jFIFO(DATAOUT, full, empty, clock, reset, wn, rn, DATAIN);
  output reg [7:0] DATAOUT;
  output reg full, empty;
  input [7:0] DATAIN;
  input clock, reset, wn, rn;
  
  reg [2:0] state;
  reg [2:0] wptr, rptr;
  reg [7:0] memory [7:0];
  reg [3:0] count; // 8深度FIFO，count范围0~8
  
  // FSM状态定义
  localparam IDLE = 3'b000;
  localparam WRITE = 3'b001;
  localparam READ = 3'b010;
  
  always @(posedge clock) begin
    if (reset) begin
      // 简化内存初始化
      integer i;
      for(i=0; i<8; i=i+1) memory[i] <= 0;
      DATAOUT <= 0; wptr <= 0; rptr <= 0; state <= IDLE;
      count <= 0;
      full <= 0; empty <= 1;
    end
    else begin
      case (state)
        IDLE: begin
          if (wn & !full)
            state <= WRITE;
          else if (rn & !empty)
            state <= READ;
        end
        
        WRITE: begin
          memory[wptr] <= DATAIN;
          wptr <= wptr + 1;
          count <= count + 1;
          state <= IDLE;
        end
        
        READ: begin
          DATAOUT <= memory[rptr];
          rptr <= rptr + 1;
          count <= count - 1;
          state <= IDLE;
        end
      endcase
      
      // 用计数器判断满/空，逻辑更严谨
      full <= (count == 8) ? 1 : 0;
      empty <= (count == 0) ? 1 : 0;
    end
  end
endmodule

内容的提问来源于stack exchange，提问作者Kafka