Quartus中VHDL语法错误(Error 10500)求助——4位二进制数高低两位比较电路实现问题

Hey there! Let's fix up your VHDL code and get rid of those syntax errors, while sticking to your assignment's no-process rule.

What's Causing the Error 10500? #

The core issue is a simple syntax mistake in how you're using the logical NOT operator. In VHDL, not must come before the signal you want to invert—writing a1 not or b1 not is backwards, which is why Quartus is throwing those syntax errors at you.

Step 1: Fix the Syntax & Use Your Simplified Equation #

You already did the hard work of deriving a simplified logical expression for gt:
gt= A0B1' + A0B1'B0' + A1A0B0'

Let's convert this to valid VHDL syntax, making sure not is placed correctly:

Full Corrected Code #

----------------------------------
--Written by K Moore
--HW 2
--9/8/2021
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--import libraries
entity HW_two is
port (a1 :in std_logic;
a0 :in std_logic;
b1 :in std_logic;
b0 :in std_logic;
gt :out std_logic);
end HW_two;
--Unsimplified equation
--A1'A0B1'B0'+ A1A0'B1'B0' + A1A0'B1'B0 + A1A0B1'B0' + A1A0B1'B0 + A1A0B1B0' = gt
--Simplified equation => gt= A0B1' + A0B1'B0' + A1A0B0'
architecture compare of HW_two is
begin
-- Corrected syntax using your simplified logical expression
gt <= (a0 and not b1) or (a0 and not b1 and not b0) or (a1 and a0 and not b0);

-- Optional further optimization: (a0 and not b1) already includes (a0 and not b1 and not b0)
-- Uncomment the line below to simplify even more
-- gt <= (a0 and not b1) or (a1 and a0 and not b0);
end compare;

Key Changes Made: #

• All not operators are now placed before the signals they invert (e.g., not b1 instead of b1 not), fixing the syntax errors.
• We're using your simplified equation instead of the long unsimplified one, making the code much easier to read and maintain.
• Added an optional optimization note: the term (a0 and not b1 and not b0) is redundant because it's already covered by (a0 and not b1) (when b0 is low, the first term includes this case). You can uncomment the optimized line to make the code even cleaner without changing functionality.

This code will compile without syntax errors in Quartus, uses pure combinational logic (no process statements), and meets your assignment's requirement of comparing the upper two bits (a1, a0) against the lower two bits (b1, b0) to output 1 when the upper bits are larger.

内容的提问来源于stack exchange，提问作者Kenzie Moore