如何在emitVerilog执行时访问Chisel模块变量并写入文件？

方案1：模块实例化时直接暴露延迟值 #

利用Chisel模块的Scala类特性，让顶层和子模块各自计算并暴露延迟属性，Driver中直接访问即可：

1. 子模块定义延迟属性

class SubModule1(subParams: SubParam1, hardcodedVal: Int) extends Module {
  val io = IO(...)
  // 根据子模块参数和硬编码值计算延迟
  lazy val latency: Int = {
    // 示例逻辑：比如基于配置的流水线级数 + 硬编码的组合逻辑延迟
    subParams.pipelineStages + hardcodedVal
  }
  // 子模块硬件逻辑...
}

2. 顶层模块聚合延迟

class MyTopModule(topParams: TopParameterSet) extends Module {
  val io = IO(...)
  
  // 实例化子模块
  val sub1 = Module(new SubModule1(topParams.sub1Params, 2)) // 硬编码值2
  val sub2 = Module(new SubModule2(topParams.sub2Params, 1)) // 硬编码值1
  
  // 顶层自身延迟 + 子模块延迟总和
  lazy val totalLatency: Int = {
    val topCombLatency = 1 // 顶层组合逻辑延迟
    topCombLatency + sub1.latency + sub2.latency
  }
  // 顶层硬件连接逻辑...
}

3. Driver中读取并写入文件

object MyModuleDriver extends App {
  val inputParams = TopParameterSet(...) // 输入配置参数
  val topModule = Module(new MyTopModule(inputParams))
  
  // 直接获取计算好的延迟
  val latency = topModule.totalLatency
  
  // 将参数和延迟写入文件
  import java.io.PrintWriter
  val writer = new PrintWriter("module_config_with_latency.txt")
  writer.println(s"Input Parameters: $inputParams")
  writer.println(s"Expected Total Latency: $latency")
  writer.close()
  
  // 生成Verilog
  emitVerilog(topModule, args)
}

方案2：利用FIRRTL Annotation传递延迟信息 #

如果延迟计算依赖硬件构建后的细节（如FIRRTL层级结构），可以通过Annotation机制在模块构建时标记延迟，Driver阶段提取：

1. 子模块添加延迟Annotation

class SubModule1(subParams: SubParam1, hardcodedVal: Int) extends Module {
  val io = IO(...)
  val latency = subParams.pipelineStages + hardcodedVal
  
  // 添加延迟Annotation
  annotate(new ChiselAnnotation {
    override def toFirrtl = firrtl.annotations.StringAnnotation(
      s"module_latency:$latency", this.getClass.getName
    )
  })
}

2. Driver中提取Annotation并计算总延迟

object MyModuleDriver extends App {
  val inputParams = TopParameterSet(...)
  val circuit = Driver.elaborate(() => new MyTopModule(inputParams))
  
  // 从所有Annotation中提取延迟值
  val subLatencies = circuit.annotations.collect {
    case ann: firrtl.annotations.StringAnnotation if ann.value.startsWith("module_latency:") =>
      ann.value.split(":")(1).toInt
  }
  val totalLatency = subLatencies.sum + 1 // 加上顶层自身延迟
  
  // 写入文件逻辑同方案1
  val writer = new PrintWriter("module_config_with_latency.txt")
  writer.println(s"Input Parameters: $inputParams")
  writer.println(s"Expected Total Latency: $totalLatency")
  writer.close()
  
  emitVerilog(circuit, args)
}

方案3：自定义FIRRTL Pass计算延迟（依赖编译后信息） #

如果延迟必须在FIRRTL优化后确定（如依赖自动插入的寄存器），可以编写自定义Pass计算并输出延迟：

1. 自定义FIRRTL Pass

class LatencyCalcPass extends firrtl.Pass {
  override def name = "LatencyCalculationPass"
  
  override def run(circuit: firrtl.Circuit): firrtl.Circuit = {
    // 遍历FIRRTL电路结构，计算总延迟（示例逻辑，需根据实际电路调整）
    val totalLatency = 0 // 替换为实际计算逻辑
    
    // 将延迟写入临时文件
    val writer = new java.io.PrintWriter("latency_temp.txt")
    writer.println(totalLatency)
    writer.close()
    circuit
  }
}

2. Driver中调用Pass并读取结果

object MyModuleDriver extends App {
  val inputParams = TopParameterSet(...)
  // 注册自定义Pass
  val customTransforms = Seq(new LatencyCalcPass)
  
  // 生成Verilog并执行Pass
  emitVerilog(new MyTopModule(inputParams), args, transforms = customTransforms)
  
  // 读取临时文件中的延迟值
  val latency = scala.io.Source.fromFile("latency_temp.txt").mkString.toInt
  
  // 写入最终配置文件
  val writer = new PrintWriter("module_config_with_latency.txt")
  writer.println(s"Input Parameters: $inputParams")
  writer.println(s"Expected Total Latency: $latency")
  writer.close()
  
  // 清理临时文件
  new java.io.File("latency_temp.txt").delete()
}

内容的提问来源于stack exchange，提问作者ftr