Nexys3 FPGA板上VHDL倒计时器在59与68间跳变问题求助

核心问题定位 #

你的倒计时器出现从59跳至68并循环的问题，根源在于计数进程的逻辑结构错误，同时存在信号初始化、端口类型的小问题：

1. 计数进程的时钟与复位逻辑完全错误 #

原代码中，将clk_o的上升沿判断放在了rst='0'的分支内部，这意味着：

• 当rst='0'（复位有效）时，才会响应时钟沿执行计数，但复位状态下本应保持初始值，不应计数
• 当rst='1'（复位无效）时，直接将计数器重置为60，完全阻断了正常计数流程

这直接导致计数器无法正常递减，反而在复位逻辑和计数逻辑的冲突下出现异常跳变。

2. 信号a未初始化 #

信号a用于切换个位/十位的7段显示，但未设置初始值，初始状态为未知态（U），可能导致显示切换异常。

3. seg端口类型错误 #

seg是输出到7段显示器的信号，无需设置为inout，改为out即可，避免不必要的总线冲突。

修复后的完整代码 #

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity kv_zad is
  port(
    rst, clk: in std_logic;
    an: out std_logic_vector(3 downto 0) := "1100";
    seg: out std_logic_vector(6 downto 0) := "0000000"
  );
end kv_zad;

architecture Behavioral of kv_zad is
  signal temp_jed: std_logic_vector(3 downto 0);
  signal temp_dek: std_logic_vector(3 downto 0);
  signal clk_o: std_logic;
  signal clk_rf: std_logic;
  signal a: std_logic := '0'; -- 初始化信号a为低电平
  begin
    s1: entity work.freqGen generic map(100_000_000) port map(clk, clk_o);
    s2: entity work.freqGen generic map(500_000) port map(clk, clk_rf);

    -- 切换显示的时钟进程
    process(clk_rf)
    begin
      if (clk_rf'event and clk_rf='1') then
        a <= not a;
      end if;
    end process;

    -- 修正后的计数进程：异步复位结构
    process(rst, clk_o)
    begin
      -- 复位有效时，设置初始值60（十位0110，个位0000）
      if (rst = '1') then -- 若Nexys3复位为低电平有效，改为rst='0'
        temp_jed <= "0000";
        temp_dek <= "0110";
      elsif (clk_o'event and clk_o='1') then
        -- 计数逻辑：从60递减到0，到0后保持
        if (temp_jed = "0000" and temp_dek = "0000") then
          temp_jed <= "0000";
          temp_dek <= "0000";
        elsif (temp_jed = "0000") then
          temp_dek <= temp_dek - 1;
          temp_jed <= "1001";
        else
          temp_jed <= temp_jed - 1;
        end if;
      end if;
    end process;

    -- 7段显示器选通控制
    with a select
      an <= "1110" when '0', -- 选通个位
            "1101" when '1'; -- 选通十位

    -- 7段显示译码逻辑
    process(a, temp_jed, temp_dek) -- 添加a到敏感列表，确保切换时立即更新
    begin
      if (a='0') then
        case temp_jed is
          when "0000" => seg <= "0000001";
          when "0001" => seg <= "1001111";
          when "0010" => seg <= "0010010";
          when "0011" => seg <= "0000110";
          when "0100" => seg <= "1101100";
          when "0101" => seg <= "0100100";
          when "0110" => seg <= "0100000";
          when "0111" => seg <= "0001111";
          when "1000" => seg <= "0000000";
          when "1001" => seg <= "0000100";
          when others => seg <= "0110000";
        end case;
      elsif (a='1') then
        case temp_dek is
          when "0000" => seg <= "0000001";
          when "0001" => seg <= "1001111";
          when "0010" => seg <= "0010010";
          when "0011" => seg <= "0000110";
          when "0100" => seg <= "1101100";
          when "0101" => seg <= "0100100";
          when "0110" => seg <= "0100000";
          when others => seg <= "0110000";
        end case;
      end if;
    end process;
end Behavioral;

额外注意事项 #

1. 复位电平确认：Nexys3开发板的复位按钮通常是低电平有效，如果修复后仍有问题，将计数进程中的rst='1'改为rst='0'。
2. freqGen模块验证：确保freqGen模块能正确生成1Hz的clk_o（用于秒计数）和合适频率的clk_rf（用于7段显示切换，建议100Hz以上，避免闪烁）。
3. 7段显示共阴/共阳确认：你的译码逻辑是共阴极7段显示的编码，Nexys3的7段显示器是共阴极，所以编码是正确的。

内容的提问来源于stack exchange，提问作者Goran Orsolic