DE1-SoC FPGA密码门锁按键触发直接跳至S8问题排查求助
FPGA密码门锁系统状态跳转异常问题
我正在DE1-SoC FPGA开发板上实现一款密码验证门锁系统:
- 预设有效密码为123、122、121,输入正确后门锁解锁
- 按键映射:KEY0对应数字'1',KEY1对应数字'2',KEY2对应数字'3',KEY3对应数字'4'
- 复位信号RST分配至SW0,开发板按键为低电平有效
- 状态跳转逻辑参考状态图:

当前遇到异常:初始处于S0状态时,按下KEY0按键,系统会直接跳至S8状态(可通过七段显示器HEX0、HEX1的显示确认)。请问我的Verilog代码是否存在问题?
以下是我的Verilog代码:
module rewardsys(KEY0,KEY1,KEY2,KEY3,HEX0,HEX1,RST); input KEY0,KEY1,KEY2,KEY3,RST; output reg [6:0] HEX0,HEX1; parameter s0=4'b0000; parameter s1=4'b0001; parameter s2=4'b0010; parameter s3=4'b0011; parameter s4=4'b0100; parameter s5=4'b0101; parameter s6=4'b0110; parameter s7=4'b0111; parameter s8=4'b1000; reg[3:0] cstate,nstate; always@(posedge KEY0,posedge KEY1,posedge KEY2,posedge KEY3,negedge RST) begin if(RST==0) cstate<=s0; else cstate<=nstate; end always @ (posedge KEY0,posedge KEY1, posedge KEY2, posedge KEY3) begin case(cstate) s0: begin //display S0 HEX1=7'b0010010; HEX0=7'b1000000; if(KEY0==0) nstate=s1; else if ((KEY1==0) | (KEY2==0) | (KEY3==0)) nstate=s6; else nstate=s0; end s1: begin //display S1 HEX1=7'b0010010; HEX0=7'b1111001; if(KEY1==0) nstate=s2; else if ((KEY0==0) | (KEY2==0) | (KEY3==0)) nstate=s7; else nstate=s1; end s2: begin //display S2 HEX1=7'b0010010; HEX0=7'b0100100; if(KEY2==0) nstate=s3; else if(KEY1==0) nstate=s4; else if(KEY0==0) nstate=s5; else if(KEY3==0) nstate=s8; else nstate=s2; end s3: begin //display S3 HEX1=7'b0010010; HEX0=7'b0110000; end s4: begin // display S4 HEX1=7'b0010010; HEX0=7'b0011001; end s5: begin //display S5 HEX1=7'b0010010; HEX0=7'b0010010; end s6: begin //display S6 HEX1=7'b0010010; HEX0=7'b0000010; if ((KEY0==0) | (KEY1==0) | (KEY2==0) | (KEY3==0)) nstate=s7; else nstate=s6; end s7: begin //display S7 HEX1=7'b0010010; HEX0=7'b1111000; if ((KEY0==0) | (KEY1==0) | (KEY2==0) | (KEY3==0)) nstate=s8; else nstate=s7; end s8: begin //display S8 HEX1=7'b0010010; HEX0=7'b0000000; nstate=s8; end default: nstate=s0; endcase end endmodule
感谢您的帮助!
内容的提问来源于stack exchange,提问作者IRFAN AZEEZ
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