Verilog有限状态机实现三连续1序列检测器的语法错误排查求助

Let's break down and fix the issues in your Verilog code step by step:

1. The Root Cause of Syntax Errors & Duplicate Default Cases #

Your first set of errors (syntax error near ; and default case should appear only once) comes directly from adding semicolons at the end of your define directives.

In Verilog, define is a text-preprocessing directive—when you write define S0 3'd0;, the semicolon becomes part of the macro. When the preprocessor replaces S0 in your case statements, you end up with invalid syntax like 3'd0;: if(r) ..., which breaks the structure of your case block. This confusion also makes the parser incorrectly detect multiple default cases.

Fix: Remove all semicolons from your macro definitions:

`define S0 3'd0
`define S1 3'd1
`define S2 3'd2
`define S3 3'd3
`define S4 3'd4

2. Illegal Timing Control in Combinational Logic #

You used repeat(1) @(posedge clk); inside the combinational always @(stanje or r or in) block. This is invalid because combinational logic blocks cannot contain timing control statements (like @(posedge clk)). Beyond syntax, this logic also doesn't match your requirement: you want the circuit to stop and wait for a reset, not automatically reset after a clock cycle.

Fix: Modify the S4 state logic to stay in the stop state until the reset signal is activated:

`S4: sledece_stanje = `S4; // Hold the stop state until reset

3. Misaligned Reset Logic #

Your original code used the r signal as a start trigger instead of a reset. According to your requirement, the reset should restart the detector after it stops. We need to prioritize reset logic above all state transitions: whenever r is active, the circuit should immediately return to the initial state S0.

Fix: Add a top-level reset check before your case statement, and adjust state transitions to match the sequence detection flow:

always @(stanje or r or in) begin
    if(r) begin
        sledece_stanje = `S0; // Reset forces return to initial state
    end else begin
        case(stanje)
            `S0: sledece_stanje = in ? `S1 : `S0; // Wait for first 1
            `S1: sledece_stanje = in ? `S2 : `S0; // Wait for second 1
            `S2: sledece_stanje = in ? `S4 : `S0; // Wait for third 1 (trigger stop)
            `S4: sledece_stanje = `S4; // Hold stop state
            default: sledece_stanje = `S0;
        endcase
    end
end

4. Bonus: Best Practice for Sequential Logic #

In your sequential state update block, use non-blocking assignment (<=) instead of blocking assignment (=). This ensures proper simulation behavior and matches how hardware synthesizes sequential logic:

always @(posedge clk) begin 
    stanje <= sledece_stanje; 
end

Full Corrected Code #

`timescale 1ns / 1ps 
`define S0 3'd0
`define S1 3'd1
`define S2 3'd2
`define S4 3'd3 // Simplified: we don't need S3 for 3-consecutive-1s detection
module kolo1(out,in,r,clk); 
output out; 
reg out; 
input in,r,clk; 
reg [2:0] stanje,sledece_stanje; 

initial begin 
    stanje=`S0; 
    sledece_stanje=`S0; 
    out=0; 
end 

always @(stanje or r or in) begin
    if(r) begin
        sledece_stanje = `S0;
    end else begin
        case(stanje)
            `S0: sledece_stanje = in ? `S1 : `S0;
            `S1: sledece_stanje = in ? `S2 : `S0;
            `S2: sledece_stanje = in ? `S4 : `S0;
            `S4: sledece_stanje = `S4;
            default: sledece_stanje = `S0;
        endcase
    end
end 

always @(posedge clk) begin 
    stanje <= sledece_stanje;
end 

always @(stanje) begin 
    case(stanje)
        `S0,`S1,`S2: out=0;
        `S4: out=1;
        default: out=0;
    endcase 
end 

endmodule 

module stimulus; 
reg clk,in,res; 
wire out; 
kolo1 k1(out,in,res,clk); 

initial clk=1'b0; 
always #2 clk=~clk; 

initial begin 
    $monitor($time,"out=%b in=%b res=%b clk=%b",out,in,res,clk); 
    in=0;res=0;
    #5 in=1;       // First 1
    #4 in=1;       // Second 1
    #4 in=1;       // Third 1: out should go high
    #8 res=1;      // Reset: out goes low, detector restarts
    #4 res=0;
    #4 in=0;
    #4 in=1;       // Restart detection with first 1
    #30 $finish; 
end 
endmodule

This code will correctly detect three consecutive 1s, stop (hold out=1) until the reset signal is activated, and then restart detection.

内容的提问来源于stack exchange，提问作者narutouzumaki 99