Cyclone IV EP4CE22上VHDL乒乓游戏显示更新异常问题
乒乓游戏VGA显示异常问题排查与解决
在Cyclone IV FPGA(EP4CE22)上使用VHDL实现乒乓游戏,采用ModelSim作为仿真工具。完成基础游戏逻辑开发后,遇到显示无法正确更新的问题:球和paddle位置固定或闪烁,疑似时序或显示更新方式存在问题。
VHDL代码实现
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- entity start entity PingPongGame is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; vga_hsync : out STD_LOGIC; vga_vsync : out STD_LOGIC; vga_red, vga_green, vga_blue : out STD_LOGIC_VECTOR(7 downto 0); paddle_up, paddle_down : in STD_LOGIC); end PingPongGame; -- entity end --architecture start architecture Behavioral of PingPongGame is signal h_counter : integer range 0 to 799 := 0; signal v_counter : integer range 0 to 524 := 0; signal row, col : integer range 0 to 639 := 0; signal ball_x, ball_y, paddle_y : integer range 0 to 479 := 0; signal ball_x_velocity, ball_y_velocity : integer := 1; signal ball_color, paddle_color, background_color : STD_LOGIC_VECTOR(7 downto 0); signal ball_visible, paddle_visible : STD_LOGIC := '0'; begin -- VGA timing process VGA_TIMING: process (clk, reset) begin if reset = '1' then h_counter <= 0; v_counter <= 0; row <= 0; col <= 0; elsif rising_edge(clk) then if h_counter < 799 then h_counter <= h_counter + 1; else h_counter <= 0; if v_counter < 524 then v_counter <= v_counter + 1; else v_counter <= 0; end if; end if; end if; end process; -- Synchronize VGA signals vga_hsync <= '1' when (h_counter < 96) else '0'; vga_vsync <= '1' when (v_counter < 2) else '0'; -- Calculate row and col positions row <= v_counter - 2; col <= h_counter - 96; -- Ball, paddle, and background colors ball_color <= "11110000"; -- Example color for the ball (adjust as needed) paddle_color <= "00001111"; -- Example color for the paddle (adjust as needed) background_color <= "00000000"; -- Example background color (adjust as needed) -- Game logic for ball movement and collision detection process (clk) begin if rising_edge(clk) then if row = ball_y and col = ball_x then ball_visible <= '1'; else ball_visible <= '0'; end if; if row >= paddle_y and row < paddle_y + 32 and col = 10 then paddle_visible <= '1'; else paddle_visible <= '0'; end if; if ball_visible = '1' then ball_x <= ball_x + ball_x_velocity; ball_y <= ball_y + ball_y_velocity; -- Collision detection with top and bottom boundaries if ball_y <= 0 or ball_y >= 472 then ball_y_velocity <= -ball_y_velocity; -- Reverse vertical velocity end if; -- Collision detection with paddle if col = 10 and paddle_visible = '1' then ball_x_velocity <= -ball_x_velocity; -- Reverse horizontal velocity end if; -- Scoring logic (ball goes out of bounds) if ball_x <= 0 or ball_x >= 632 then ball_x <= 320; ball_y <= 240; ball_x_velocity <= 1; -- Reset velocity ball_y_velocity <= 1; -- Reset velocity end if; end if; -- Paddle control if paddle_up = '1' and paddle_y > 0 then paddle_y <= paddle_y - 1; elsif paddle_down = '1' and paddle_y < 448 then paddle_y <= paddle_y + 1; end if; end if; end process; -- Output VGA colors based on game logic process (ball_visible, paddle_visible) begin if ball_visible = '1' then vga_red <= ball_color; vga_green <= ball_color; vga_blue <= ball_color; elsif paddle_visible = '1' then vga_red <= paddle_color; vga_green <= paddle_color; vga_blue <= paddle_color; else vga_red <= background_color; vga_green <= background_color; vga_blue <= background_color; end if; end process; end Behavioral; --architecture end
已尝试的排查步骤
- 检查VGA时序信号,确认无误;
- 验证球与paddle的移动逻辑,运行符合预期;
- 确认VGA控制器针对Cyclone IV FPGA配置正确。
问题更新
问题已解决
经详细排查,该显示更新异常问题并非出自VHDL代码本身,而是与FPGA配置及ModelSim仿真相关。
内容的提问来源于stack exchange,提问作者user19026118
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